EP20K400EFI672-2X Datasheet, PDF (2/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
Table 2. Additional APEX 20K Device Features Note (1)
Feature
Maximum system
gates
Typical gates
LEs
ESBs
Maximum
RAM bits
Maximum
macrocells
Maximum user I/O
pins
EP20K300E
728,000
300,000
11,520
72
147,456
1,152
408
EP20K400
1,052,000
400,000
16,640
104
212,992
1,664
502
EP20K400E EP20K600E EP20K1000E EP20K1500E
1,052,000 1,537,000 1,772,000 2,392,000
400,000
16,640
104
212,992
600,000
24,320
152
311,296
1,000,000
38,400
160
327,680
1,500,000
51,840
216
442,368
1,664
2,432
2,560
3,456
488
588
708
808
Note to Tables 1 and 2:
(1) The embedded IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan circuitry contributes up to
57,000 additional gates.
Additional
Features
■ Designed for low-power operation
– 1.8-V and 2.5-V supply voltage (see Table 3)
– MultiVolt^TM I/O interface support to interface with 1.8-V, 2.5-V,
3.3-V, and 5.0-V devices (see Table 3)
– ESB offering programmable power-saving mode
Table 3. APEX 20K Supply Voltages
Feature
EP20K100
EP20K200
EP20K400
Internal supply voltage (V_CCINT)
2.5 V
MultiVolt I/O interface voltage levels (V_CCIO) 2.5 V, 3.3 V, 5.0 V
Device
EP20K30E
EP20K60E
EP20K100E
EP20K160E
EP20K200E
EP20K300E
EP20K400E
EP20K600E
EP20K1000E
EP20K1500E
1.8 V
1.8 V, 2.5 V, 3.3 V, 5.0 V (1)
Note to Table 3:
(1) APEX 20KE devices can be 5.0-V tolerant by using an external resistor.
2
Altera Corporation