EP20K400EFI672-2X Datasheet, PDF (65/117 Pages) Altera Corporation – Programmable Logic Device Family

APEX 20K Programmable Logic Device Family Data Sheet
1 For DC Operating Specifications on APEX 20KE I/O standards,
please refer to Application Note 117 (Using Selectable I/O Standards
in Altera Devices).
Table 30. APEX 20KE Device Capacitance Note (15)
Symbol
Parameter
C_IN
C_INCLK
C_OUT
Input capacitance
Input capacitance on
dedicated clock pin
Output capacitance
Conditions
V_IN = 0 V, f = 1.0 MHz
V_IN = 0 V, f = 1.0 MHz
V_OUT = 0 V, f = 1.0 MHz
Min Max Unit
8
pF
12
pF
8
pF
Notes to Tables 27 through 30:
(1) See the Operating Requirements for Altera Devices Data Sheet.
(2) Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 5.75 V for
input currents less than 100 mA and periods shorter than 20 ns.
(3) Numbers in parentheses are for industrial-temperature-range devices.
(4) Maximum V_CC rise time is 100 ms, and V_CC must rise monotonically.
(5) Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to the voltage
shown in the following table based on input duty cycle for input currents less than 100 mA. The overshoot is
dependent upon duty cycle of the signal. The DC case is equivalent to 100% duty cycle.
Vin
Max. Duty Cycle
4.0V
100% (DC)
4.1
90%
4.2
50%
4.3
30%
4.4
17%
4.5
10%
(6) All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before V_CCINT and V_CCIO are
powered.
(7) Typical values are for T_A = 25° C, V_CCINT = 1.8 V, and V_CCIO = 1.8 V, 2.5 V or 3.3 V.
(8) These values are specified under the APEX 20KE device recommended operating conditions, shown in Table 24 on
page 60.
(9) Refer to Application Note 117 (Using Selectable I/O Standards in Altera Devices) for the V_IH, V_IL, V_OH, V_OL, and I_I
parameters when VCCIO = 1.8 V.
(10) The APEX 20KE input buffers are compatible with 1.8-V, 2.5-V and 3.3-V (LVTTL and LVCMOS) signals.
Additionally, the input buffers are 3.3-V PCI compliant. Input buffers also meet specifications for GTL+, CTT, AGP,
SSTL-2, SSTL-3, and HSTL.
(11) The I_OH parameter refers to high-level TTL, PCI, or CMOS output current.
(12) The I_OL parameter refers to low-level TTL, PCI, or CMOS output current. This parameter applies to open-drain pins
as well as output pins.
(13) This value is specified for normal device operation. The value may vary during power-up.
(14) Pin pull-up resistance values will be lower if an external source drives the pin higher than V_CCIO.
(15) Capacitance is sample-tested only.
Figure 33 shows the relationship between V_CCIO and V_CCINT for 3.3-V PCI
compliance on APEX 20K devices.
Altera Corporation
65