EP2S90F1020C4 Datasheet, PDF (86/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet

I/O Structure
When using the IOE for DDR inputs, the two input registers clock double
rate input data on alternating edges. An input latch is also used in the IOE
for DDR input acquisition. The latch holds the data that is present during
the clock high times. This allows both bits of data to be synchronous with
the same clock edge (either rising or falling). Figure 2–52 shows an IOE
configured for DDR input. Figure 2–53 shows the DDR input timing
diagram.
Figure 2–52. Stratix II IOE in DDR Input I/O Configuration Notes (1), (2), (3)
ioe_clk[7..0]
Column, Row,
or Local
Interconnect
DQS Local
Bus (2)
VCCIO
To DQS Logic
Block (3)
PCI Clamp (4)
VCCIO
Programmable
Pull-Up
Resistor
sclr/spreset
clkin
ce_in
aclr/apreset
Input Pin to
Input RegisterDelay
Input Register
D
Q
ENA
CLRN/PRN
On-Chip
Termination
Bus-Hold
Circuit
Chip-Wide Reset
Input Register
D
Q
Latch
D
Q
ENA
CLRN/PRN
ENA
CLRN/PRN
Notes to Figure 2–52:
(1) All input signals to the IOE can be inverted at the IOE.
(2) This signal connection is only allowed on dedicated DQ function pins.
(3) This signal is for dedicated DQS function pins only.
(4) The optional PCI clamp is only available on column I/O pins.
2–78
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007