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EP2S90F1020C4 Datasheet, PDF (57/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet | |||
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Stratix II Architecture
global clock networks can also be driven by internal logic for internally
generated global clocks and asynchronous clears, clock enables, or other
control signals with large fanout. Figure 2â31 shows the 16 dedicated CLK
pins driving global clock networks.
Figure 2â31. Global Clocking
CLK[15..12]
Global Clock [15..0]
CLK[3..0]
Global Clock [15..0] CLK[11..8]
CLK[7..4]
Regional Clock Network
There are eight regional clock networks RCLK[7..0] in each quadrant of
the Stratix II device that are driven by the dedicated CLK[15..0] input
pins, by PLL outputs, or by internal logic. The regional clock networks
provide the lowest clock delay and skew for logic contained in a single
quadrant. The CLK clock pins symmetrically drive the RCLK networks in
a particular quadrant, as shown in Figure 2â32.
Altera Corporation
May 2007
2â49
Stratix II Device Handbook, Volume 1
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