EP2S90F1020C4 Datasheet, PDF (29/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet

Stratix II Architecture
Figure 2–15. Register Chain within an LAB Note (1)
Combinational
Logic
adder0
adder1
Combinational
Logic
adder0
adder1
reg_chain_in
From Previous ALM
Within The LAB
DQ
reg0
To general or
local routing
To general or
local routing
DQ
reg1
DQ
reg0
To general or
local routing
To general or
local routing
To general or
local routing
To general or
local routing
DQ
reg1
To general or
local routing
To general or
local routing
reg_chain_out
To Next ALM
within the LAB
Note to Figure 2–15:
(1) The combinational or adder logic can be utilized to implement an unrelated, un-registered function.
See the “MultiTrack Interconnect” on page 2–22 section for more
information on register chain interconnect.
Altera Corporation
May 2007
2–21
Stratix II Device Handbook, Volume 1