EP2S90F1020C4 Datasheet, PDF (164/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet

Timing Model
1 The performance numbers in Table 5–36 are extracted from the
Quartus II software version 5.1 SP1.
Table 5–36. Stratix II Performance Notes (Part 1 of 6) Note (1)
Resources Used
Performance
Applications
ALUTs
LE
16-to-1 multiplexer (4) 21
32-to-1 multiplexer (4) 38
16-bit counter
16
64-bit counter
64
TriMatrix Simple dual-port RAM 0
Memory 32 × 18 bit
M512
FIFO 32 x 18 bit
22
block
TriMatrix Simple dual-port RAM 0
Memory 128 x 36 bit (8)
M4K
True dual-port RAM
0
block
128 × 18 bit (8)
FIFO
22
128 × 36 bit
Simple dual-port RAM 0
128 × 36 bit (9)
True dual-port RAM
0
128 × 18 bit (9)
TriMatrix
Memory
Blocks
DSP
Blocks
-3
Speed
Grade
(2)
0
0 654.87
0
0 519.21
0
0 566.57
0
0 244.31
1
0 500.00
1
0 500.00
1
0 540.54
1
0 540.54
1
0 530.22
1
0 475.28
1
0 475.28
-3
Speed
Grade
(3)
625.0
473.26
538.79
232.07
476.19
476.19
515.46
515.46
499.00
453.30
453.30
-4
Speed
Grade
523.83
464.25
489.23
209.11
434.02
434.78
469.48
469.48
469.48
413.22
413.22
-5
Speed Unit
Grade
460.4 MHz
384.17 MHz
421.05 MHz
181.38 MHz
373.13 MHz
373.13 MHz
401.60 MHz
401.60 MHz
401.60 MHz
354.10 MHz
354.10 MHz
5–28
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011