EP2S90F1020C4 Datasheet, PDF (102/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet

I/O Structure
Table 2–18 summarizes Stratix II MultiVolt I/O support.
Table 2–18. Stratix II MultiVolt I/O Support Note (1)
V_CCIO (V)
1.2
1.5
1.8
2.5
3.3
Input Signal (V)
Output Signal (V)
1.2 1.5
1.8
2.5
3.3
1.2 1.5 1.8 2.5 3.3 5.0
(4) v (2) v (2) v (2) v (2) v (4)
(4)
v
v
v (2) v (2) v (3) v
(4)
v
v
v (2) v (2) v (3) v (3) v
(4)
v
v
v (3) v (3) v (3) v
(4)
v
v
v (3) v (3) v (3) v (3) v v
Notes to Table 2–18:
(1) To drive inputs higher than V_CCIO but less than 4.0 V, disable the PCI clamping diode and select the Allow LVTTL
and LVCMOS input levels to overdrive input buffer option in the Quartus II software.
(2) The pin current may be slightly higher than the default value. You must verify that the driving device’s V_{O L}
maximum and V_{O H} minimum voltages do not violate the applicable Stratix II V_{I L} maximum and V_{I H} minimum
voltage specifications.
(3) Although V_CCIO specifies the voltage necessary for the Stratix II device to drive out, a receiving device powered at
a different level can still interface with the Stratix II device if it has inputs that tolerate the V_CCIO value.
(4) Stratix II devices do not support 1.2-V LVTTL and 1.2-V LVCMOS. Stratix II devices support 1.2-V HSTL.
The TDO and nCEO pins are powered by V_CCIO of the bank that they reside
in. TDO is in I/O bank 4 and nCEO is in I/O bank 7.
Ideally, the V_CC supplies for the I/O buffers of any two connected pins are
at the same voltage level. This may not always be possible depending on
the V_CCIO level of TDO and nCEO pins on master devices and the
configuration voltage level chosen by VCCSEL on slave devices. Master
and slave devices can be in any position in the chain. Master indicates that
it is driving out TDO or nCEO to a slave device.
For multi-device passive configuration schemes, the nCEO pin of the
master device drives the nCE pin of the slave device. The VCCSEL pin on
the slave device selects which input buffer is used for nCE. When VCCSEL
is logic high, it selects the 1.8-V/1.5-V buffer powered by V_CCIO. When
VCCSEL is logic low it selects the 3.3-V/2.5-V input buffer powered by
V_CCPD. The ideal case is to have the V_CCIO of the nCEO bank in a master
device match the VCCSEL settings for the nCE input buffer of the slave
device it is connected to, but that may not be possible depending on the
application. Table 2–19 contains board design recommendations to
ensure that nCEO can successfully drive nCE for all power supply
combinations.
2–94
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007