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EP2S90F1020C4 Datasheet, PDF (153/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet | |||
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DC & Switching Characteristics
Bus Hold Specifications
Table 5â29 shows the Stratix II device family bus hold specifications.
Table 5â29. Bus Hold Parameters
Parameter Conditions
1.2 V
1.5 V
VCCIO Level
1.8 V
2.5 V
3.3 V Unit
Min Max Min Max Min Max Min Max Min Max
Low
VIN > VIL
22.5
25.0
30.0
50.0
70.0
μA
sustaining (maximum)
current
High
VIN < VIH
â22.5
â25.0
â30.0
â50.0
â70.0
μA
sustaining (minimum)
current
Low
0 V < VIN <
120
160
200
300
500 μA
overdrive VCCIO
current
High
overdrive
current
0 V < VIN <
VCCIO
â120
â160
â200
â300
â500 μA
Bus-hold
trip point
0.45 0.95 0.50 1.00 0.68 1.07 0.70 1.70 0.80 2.00 V
On-Chip Termination Specifications
Tables 5â30 and 5â31 define the specification for internal termination
resistance tolerance when using series or differential on-chip termination.
Table 5â30. Series On-Chip Termination Specification for Top & Bottom I/O Banks (Part 1 of 2)
Notes (1), 2
Symbol
Description
Conditions
25-Ω RS
3.3/2.5
Internal series termination with
calibration (25-Ω setting)
VC C I O = 3.3/2.5 V
Internal series termination without VC CI O = 3.3/2.5 V
calibration (25-Ω setting)
Resistance Tolerance
Commercial Industrial
Max
Max
Unit
±5
±10
%
±30
±30
%
Altera Corporation
April 2011
5â17
Stratix II Device Handbook, Volume 1
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