EP2S90F1020C4 Datasheet, PDF (133/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet

Hot Socketing & Power-On Reset
I_IOPIN is the current at any user I/O pin on the device. This specification
takes into account the pin capacitance, but not board trace and external
loading capacitance. Additional capacitance for trace, connector, and
loading needs must be considered separately. For the AC specification,
the peak current duration is 10 ns or less because of power-up transients.
For more information, refer to the Hot-Socketing & Power-Sequencing
Feature & Testing for Altera Devices white paper.
A possible concern regarding hot-socketing is the potential for latch-up.
Latch-up can occur when electrical subsystems are hot-socketed into an
active system. During hot-socketing, the signal pins may be connected
and driven by the active system before the power supply can provide
current to the device's V_CC and ground planes. This condition can lead to
latch-up and cause a low-impedance path from V_CC to ground within the
device. As a result, the device extends a large amount of current, possibly
causing electrical damage. Nevertheless, Stratix II devices are immune to
latch-up when hot-socketing.
Hot Socketing
Feature
Implementation
in Stratix II
Devices
The hot socketing feature turns off the output buffer during the power-up
event (either V_CCINT, V_CCIO, or V_CCPD supplies) or power down. The hot-
socket circuit will generate an internal HOTSCKT signal when either
V_CCINT, V_CCIO, or V_CCPD is below threshold voltage. The HOTSCKT signal
will cut off the output buffer to make sure that no DC current (except for
weak pull up leaking) leaks through the pin. When V_CC ramps up very
slowly, V_CC is still relatively low even after the POR signal is released and
the configuration is finished. The CONF_DONE, nCEO, and nSTATUS pins
fail to respond, as the output buffer can not flip from the state set by the
hot socketing circuit at this low V_CC voltage. Therefore, the hot socketing
circuit has been removed on these configuration pins to make sure that
they are able to operate during configuration. It is expected behavior for
these pins to drive out during power-up and power-down sequences.
Each I/O pin has the following circuitry shown in Figure 4–1.
Altera Corporation
May 2007
4–3
Stratix II Device Handbook, Volume 1