EP2S90F1020C4 Datasheet, PDF (23/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet

Stratix II Architecture
Figure 2–11. ALM in Arithmetic Mode
carry_in
datae0
dataf0
datac
datab
dataa
datad
datae1
dataf1
4-Input
LUT
4-Input
LUT
4-Input
LUT
4-Input
LUT
adder0
DQ
reg0
adder1
DQ
reg1
carry_out
To general or
local routing
To general or
local routing
To general or
local routing
To general or
local routing
While operating in arithmetic mode, the ALM can support simultaneous
use of the adder's carry output along with combinational logic outputs. In
this operation, the adder output is ignored. This usage of the adder with
the combinational logic output provides resource savings of up to 50% for
functions that can use this ability. An example of such functionality is a
conditional operation, such as the one shown in Figure 2–12. The
equation for this example is:
R = (X < Y) ? Y : X
To implement this function, the adder is used to subtract ‘Y’ from ‘X.’ If
‘X’ is less than ‘Y,’ the carry_out signal is ‘1.’ The carry_out signal is
fed to an adder where it drives out to the LAB local interconnect. It then
feeds to the LAB-wide syncload signal. When asserted, syncload
selects the syncdata input. In this case, the data ‘Y’ drives the
syncdata inputs to the registers. If ‘X’ is greater than or equal to ‘Y,’ the
syncload signal is de-asserted and ‘X’ drives the data port of the
registers.
Altera Corporation
May 2007
2–15
Stratix II Device Handbook, Volume 1