EP2S90F1020C4 Datasheet, PDF (166/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet

Timing Model
Table 5–36. Stratix II Performance Notes (Part 3 of 6) Note (1)
Resources Used
Performance
DSP
block
Larger
designs
Applications
ALUTs
9 × 9-bit multiplier (5)
18 × 18-bit
multiplier (5)
18 × 18-bit
multiplier (7)
36 × 36-bit
multiplier (5)
36 × 36-bit multiplier
(6)
18-bit, four-tap FIR
filter
8-bit,16-tap parallel
FIR filter
8-bit, 1024-point,
streaming, three
multipliers and five
adders FFT function
8-bit, 1024-point,
streaming, four
multipliers and two
adders FFT function
8-bit, 1024-point,
single output, one
parallel FFT engine,
burst, three multipliers
and five adders FFT
function
8-bit, 1024-point,
single output, one
parallel FFT engine,
burst, four multipliers
and two adders FFT
function
0
0
0
0
0
0
58
2976
2781
984
919
TriMatrix
Memory
Blocks
DSP
Blocks
-3
Speed
Grade
(2)
0
1 430.29
0
1 410.17
0
1 450.04
0
1 250.00
0
1 410.17
0
1 410.17
0
4 259.06
22
9 398.72
22
12 398.56
5
3 425.17
5
4 427.53
-3
Speed
Grade
(3)
409.16
390.01
428.08
238.15
390.01
390.01
240.61
364.03
409.16
365.76
378.78
-4
Speed
Grade
373.13
356.12
391.23
217.48
356.12
356.12
217.15
355.23
347.22
346.98
357.14
-5
Speed Unit
Grade
320.10 MHz
305.06 MHz
335.12 MHz
186.60 MHz
305.06 MHz
305.06 MHz
185.01 MHz
306.37 MHz
311.13 MHz
292.39 MHz
307.59 MHz
5–30
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011