EP2S90F1020C4 Datasheet, PDF (218/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet

Duty Cycle Distortion
Table 5–82. Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path for -3
Devices Notes (1), (2)
Maximum DCD Based on I/O Standard of Input Feeding the DDIO Clock Port
(No PLL in Clock Path)
Row DDIO Output I/O
Standard
TTL/CMOS
SSTL-2
LVDS/
SSTL/HSTL HyperTransport
Unit
Technology
3.3 & 2.5 V 1.8 & 1.5 V 2.5 V 1.8 & 1.5 V
3.3 V
3.3-V LVTTL
260
380
145
145
3.3-V LVCMOS
210
330
100
100
2.5 V
195
315
85
85
1.8 V
150
265
85
85
1.5-V LVCMOS
255
370
140
140
SSTL-2 Class I
175
295
65
65
SSTL-2 Class II
170
290
60
60
SSTL-18 Class I
155
275
55
50
1.8-V HSTL Class I
150
270
60
60
1.5-V HSTL Class I
150
270
55
55
LVDS/ HyperTransport
180
180
180
180
technology
110
ps
65
ps
75
ps
120
ps
105
ps
70
ps
75
ps
90
ps
95
ps
90
ps
180
ps
Notes to Table 5–82:
(1) The information in Table 5–82 assumes the input clock has zero DCD.
(2) The DCD specification is based on a no logic array noise condition.
Here is an example for calculating the DCD in percentage for a DDIO
output on a row I/O on a -3 device:
If the input I/O standard is SSTL-2 and the DDIO output I/O standard is
SSTL-2 Class II, the maximum DCD is 60 ps (see Table 5–82). If the clock
frequency is 267 MHz, the clock period T is:
T = 1/ f = 1 / 267 MHz = 3.745 ns = 3745 ps
Calculate the DCD as a percentage:
(T/2 – DCD) / T = (3745ps/2 – 60ps) / 3745ps = 48.4% (for low
boundary)
(T/2 + DCD) / T = (3745 ps/2 + 60 ps) / 3745ps = 51.6% (for high
boundary)
5–82
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011