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EP2S90F1020C4 Datasheet, PDF (154/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet
Operating Conditions
Table 5–30. Series On-Chip Termination Specification for Top & Bottom I/O Banks (Part 2 of 2)
Notes (1), 2
Symbol
Description
Conditions
50-Ω RS
3.3/2.5
50-Ω RT
2.5
25-Ω RS
1.8
50-Ω RS
1.8
50-Ω RT
1.8
50−Ω RS
1.5
50-Ω RT
1.5
50−Ω RS
1.2
50-Ω RT
1.2
Internal series termination with
calibration (50-Ω setting)
Internal series termination without
calibration (50-Ω setting)
Internal parallel termination with
calibration (50-Ω setting)
Internal series termination with
calibration (25-Ω setting)
Internal series termination without
calibration (25-Ω setting)
Internal series termination with
calibration (50-Ω setting)
Internal series termination without
calibration (50-Ω setting)
Internal parallel termination with
calibration (50-Ω setting)
Internal series termination with
calibration (50-Ω setting)
Internal series termination without
calibration (50-Ω setting)
Internal parallel termination with
calibration (50-Ω setting)
Internal series termination with
calibration (50-Ω setting)
Internal series termination without
calibration (50-Ω setting)
Internal parallel termination with
calibration (50-Ω setting)
VC C I O = 3.3/2.5 V
VC C I O = 3.3/2.5 V
VC C I O = 1.8 V
VC C I O = 1.8 V
VC C I O = 1.8 V
VC C I O = 1.8 V
VC C I O = 1.8 V
VC C I O = 1.8 V
VC C I O = 1.5 V
VC C I O = 1.5 V
VC C I O = 1.5 V
VC C I O = 1.2 V
VC C I O = 1.2 V
VC C I O = 1.2 V
Resistance Tolerance
Commercial Industrial
Max
Max
Unit
±5
±10
%
±30
±30
%
±30
±30
%
±5
±10
%
±30
±30
%
±5
±10
%
±30
±30
%
±10
±15
%
±8
±10
%
±36
±36
%
±10
±15
%
±8
±10
%
±50
±50
%
±10
±15
%
Notes for Table 5–30:
(1) The resistance tolerances for calibrated SOCT and POCT are for the moment of calibration. If the temperature or
voltage changes over time, the tolerance may also change.
(2) On-chip parallel termination with calibration is only supported for input pins.
5–18
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011