EP2S90F1020C4 Datasheet, PDF (172/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet

Timing Model
Table 5–39. DSP Block Internal Timing Microparameters (Part 1 of 2)
Symbol
Parameter
-3 Speed
Grade (1)
Min
(3)
Max
-3 Speed
Grade (2)
Min
(3)
Max
-4 Speed
Grade
Min
(4)
Max
-5 Speed
Grade
Unit
Min
(3)
Max
t_{S U}
Input, pipeline, and
50
52
57
67
ps
output register setup
57
time before clock
t_H
Input, pipeline, and 180
189
206
241
ps
output register hold
206
time after clock
t_{C O}
Input, pipeline, and
0
0
0
0
0
0
0
0 ps
output register clock-
0
to-output delay
t_{I N R E G 2 P I P E 9}
Input register to DSP 1,312 2,030 1,312 2,030 1,250 2,334 1,312 2,720 ps
block pipeline register
1,312
in 9 × 9-bit mode
t_{I N R E G 2 P I P E 1 8}
Input register to DSP 1,302 2,010 1,302 2,110 1,240 2,311 1,302 2,693 ps
block pipeline register
1,302
in 18 × 18-bit mode
t_{I N R E G 2 P I P E 3 6}
Input register to DSP 1,302 2,010 1,302 2,110 1,240 2,311 1,302 2,693 ps
block pipeline register
1,302
in 36 × 36-bit mode
t_{P I P E 2 O U T R E G 2 A D D}
DSP block pipeline
register to output
register delay in two-
multipliers adder
mode
924 1,450 924 1,522 880 1,667 924 1,943 ps
924
t_{P I P E 2 O U T R E G 4 A D D} DSP block pipeline
register to output
1,134 1,850 1,134 1,942 1,080 2,127 1,134 2,479 ps
1,134
register delay in four-
multipliers adder
mode
t_{P D 9}
Combinational input 2,100 2,880 2,100 3,024 2,000 3,312 2,100 3,859 ps
to output delay for
2,100
9×9
t_{P D 1 8}
Combinational input
to output delay for
18 × 18
2,110 2,990 2,110 3,139 2,010 3,438 2,110 4,006 ps
2,110
t_{P D 3 6}
Combinational input
to output delay for
36 × 36
2,939 4,450 2,939 4,672 2,800 5,117 2,939 5,962 ps
2,939
t_{C L R}
Minimum clear pulse 2,212
2,322
2,543
2,964
ps
width
2,543
5–36
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011