EP2S90F1020C4 Datasheet, PDF (220/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet

Duty Cycle Distortion
Table 5–84. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -3
Devices (Part 2 of 2) Notes (1), (2)
Maximum DCD Based on I/O Standard of Input Feeding the DDIO
Clock Port (No PLL in the Clock Path)
DDIO Column Output I/O
Standard
TTL/CMOS
SSTL-2 SSTL/HSTL
1.2-V
HSTL
Unit
3.3/2.5 V 1.8/1.5 V 2.5 V
1.8/1.5 V
1.2 V
1.8 V
150
265
85
85
85
ps
1.5-V LVCMOS
255
370
140
140
140
ps
SSTL-2 Class I
175
295
65
65
65
ps
SSTL-2 Class II
170
290
60
60
60
ps
SSTL-18 Class I
155
275
55
50
50
ps
SSTL-18 Class II
140
260
70
70
70
ps
1.8-V HSTL Class I
150
270
60
60
60
ps
1.8-V HSTL Class II
150
270
60
60
60
ps
1.5-V HSTL Class I
150
270
55
55
55
ps
1.5-V HSTL Class II
125
240
85
85
85
ps
1.2-V HSTL
240
360
155
155
155
ps
LVPECL
180
180
180
180
180
ps
Notes to Table 5–84:
(1) Table 5–84 assumes the input clock has zero DCD.
(2) The DCD specification is based on a no logic array noise condition.
Table 5–85. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -4 & -5
Devices (Part 1 of 2) Notes (1), (2)
DDIO Column Output I/O
Standard
Maximum DCD Based on I/O Standard of Input Feeding the DDIO
Clock Port (No PLL in the Clock Path)
TTL/CMOS
SSTL-2
SSTL/HSTL
Unit
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
3.3/2.5 V
440
390
375
325
430
355
350
1.8/1.5 V
495
450
430
385
490
410
405
2.5 V
170
120
105
90
160
85
80
1.8/1.5 V
160
ps
110
ps
95
ps
100
ps
155
ps
75
ps
70
ps
5–84
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011