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EP3C10U256C6N Datasheet, PDF (83/274 Pages) Altera Corporation – Cyclone III Device Family Overview | |||
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Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Phase Shift Implementation
5â23
Fine resolution phase shifts are implemented by allowing any of the output counters
(C[4..0]) or the M counter to use any of the eight phases of the VCO as the reference
clock. This allows you to adjust the delay time with a fine resolution. Equation 5â1
shows the minimum delay time that you can insert using this method.
Equation 5â1. Fine Resolution Phase Shift
ïfine
=
T----V----C---O--
8
=
-------1-------
8fVCO
=
--------N-----------
8MfREF
Note to Equation 5â1:
(1) fREF is the input reference clock frequency
For example, if fREF is 100 MHz, N = 1, and M = 8, then fVCO = 800 MHz, and
ïfine = 156.25 ps. The PLL operating frequency defines this phase shift, a value that
depends on reference clock frequency and counter settings.
Coarse resolution phase shifts are implemented by delaying the start of the counters
for a predetermined number of counter clocks. Equation 5â2 shows the coarse phase
shift.
Equation 5â2. Coarse Resolution Phase Shift
ïcoarse
=
C------â----1--
fVCO
=
-ï¨--C-----â-----1---ï©---N---
MfREF
Note to Equation 5â2:
(1) C is the count value set for the counter delay timeâthe initial setting in the PLL usage section of the compilation
report in the Quartus II software. If the initial value is 1, C â 1 = 0° phase shift.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
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