EP3C10U256C6N Datasheet, PDF (35/274 Pages) Altera Corporation – Cyclone III Device Family Overview

December 2011
CIII51004-2.3
CIII51004-2.3
3. Memory Blocks in the Cyclone III
Device Family
Overview
The Cyclone^® III device family (Cyclone III and Cyclone III LS devices) features
embedded memory structures to address the on-chip memory needs of Altera^®
Cyclone III device family designs. The embedded memory structure consists of
columns of M9K memory blocks that you can configure to provide various memory
functions, such as RAM, shift registers, ROM, and FIFO buffers.
This chapter contains the following sections:
■ “Memory Modes” on page 3–7
■ “Clocking Modes” on page 3–14
■ “Design Considerations” on page 3–15
M9K blocks support the following features:
■ 8,192 memory bits per block (9,216 bits per block including parity)
■ Independent read-enable (rden) and write-enable (wren) signals for each port
■ Packed mode in which the M9K memory block is split into two 4.5 K single-port
RAMs
■ Variable port configurations
■ Single-port and simple dual-port modes support for all port widths
■ True dual-port (one read and one write, two reads, or two writes) operation
■ Byte enables for data input masking during writes
■ Two clock-enable control signals for each port (port A and port B)
■ Initialization file to pre-load memory content in RAM and ROM modes
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Cyclone III Device Handbook
Volume 1
December 2011
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