EP3C10U256C6N Datasheet, PDF (66/274 Pages) Altera Corporation – Cyclone III Device Family Overview

5–6
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Clock Networks
GCLK Network Clock Source Generation
Figure 5–2 shows Cyclone III device family PLLs, clock inputs, and clock control
block location for different device densities.
Figure 5–2. PLL, CLK[], DPCLK[], and Clock Control Block Locations in the Cyclone III Device Family ⁽¹⁾
DPCLK[11.10] DPCLK[9..8]
CDPCLK7
CLK[11..8]
CDPCLK6
CDPCLK0
DPCLK0
CLK[3..0]
4
DPCLK1
CDPCLK1
PLL
3
(3)
(2)
4
4
5
(2)
2
2
4
4
5
(3) 4
2
2
GCLK[19..0]
20
20
Clock Control
Block (1)
20
Clock Control
Block (1)
20
GCLK[19..0]
2
2
PLL
(3)
1
4
5
4
2
42
PLL
2
(2)
4
5
4
(2)
(3)
PLL
4
CDPCLK5
DPCLK7
CLK[7..4]
4
DPCLK6
CDPCLK4
CDPCLK2
CLK[15..12]
DPCLK[3..2] DPCLK[5..4]
CDPCLK3
Notes to Figure 5–2:
(1) There are five clock control blocks on each side.
(2) Only one of the corner CDPCLK pins in each corner can feed the clock control block at a time. You can use the other CDPCLK pins as
general-purpose I/O pins.
(3) Remote clock pins can feed PLLs over dedicated clock paths. However, these paths are not fully compensated.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation