EP3C10U256C6N Datasheet, PDF (139/274 Pages) Altera Corporation – Cyclone III Device Family Overview

Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
Design Guidelines
7–17
Figure 7–16 shows the Cyclone III device family high-speed I/O timing budget.
Figure 7–16. Cyclone III Device Family High-Speed I/O Timing Budget ⁽¹⁾
Internal Clock Period
0.5 × TCCS RSKM
SW
Note to Figure 7–16:
(1) The equation for the high-speed I/O timing budget is:
eriod = 0.5  TCCS + RSKM + SW + RSKM + 0.5  TCCS
RSKM
0.5 × TCCS
f For more information, refer to the Cyclone III Device Data Sheet and Cyclone III LS
Device Data Sheet chapters in volume 2 of the Cyclone III Device Handbook.
Design Guidelines
This section provides guidelines for designing with the Cyclone III device family.
Differential Pad Placement Guidelines
To maintain an acceptable noise level on the V_CCIO supply, you must observe some
restrictions on the placement of single-ended I/O pins in relation to differential pads.
Altera recommends that you create a Quartus II design, enter your device I/O
assignments, and compile your design to validate your pin placement. The Quartus II
software checks your pin connections with respect to the I/O assignment and
placement rules to ensure proper device operation.
f For more information about how the Quartus II software checks I/O restrictions, refer
to the I/O Management chapter in volume 2 of the Quartus II Handbook.
Board Design Considerations
This section explains how to achieve the optimal performance from the Cyclone III
device family I/O interface and ensure first-time success in implementing a
functional design with optimal signal quality. You must consider the critical issues of
controlled impedance of traces and connectors, differential routing, and termination
techniques to get the best performance from the Cyclone III device family.
Use the following general guidelines for improved signal quality:
■ Base board designs on controlled differential impedance. Calculate and compare
all parameters, such as trace width, trace thickness, and the distance between two
differential traces.
■ Maintain equal distance between traces in differential I/O standard pairs as much
as possible. Routing the pair of traces close to each other maximizes the
common-mode rejection ratio (CMRR).
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1