EP3C10U256C6N Datasheet, PDF (123/274 Pages) Altera Corporation – Cyclone III Device Family Overview

December 2011
CIII51008-4.0
CIII51008-4.0
7. High-Speed Differential Interfaces in
the Cyclone III Device Family
This chapter describes the high-speed differential I/O features and resources in the
Cyclone III device family.
High-speed differential I/O standards have become popular in high-speed interfaces
because of their significant advantages over single-ended I/O standards. The Altera^®
Cyclone^® III device family (Cyclone III and Cyclone III LS devices) supports LVDS,
BLVDS, reduced swing differential signaling (RSDS), mini-LVDS, and point-to-point
differential signaling (PPDS).
This chapter contains the following sections:
■ “High-Speed I/O Interface” on page 7–1
■ “High-Speed I/O Standards Support” on page 7–7
■ “True Output Buffer Feature” on page 7–15
■ “High-Speed I/O Timing” on page 7–16
■ “Design Guidelines” on page 7–17
■ “Software Overview” on page 7–18
High-Speed I/O Interface
Cyclone III device family I/Os are separated into eight I/O banks, as shown in
Figure 7–1. Each bank has an independent power supply. True output drivers for
LVDS, RSDS, mini-LVDS, and PPDS are on the left and right I/O banks. These I/O
standards are also supported on the top and bottom I/O banks using external
resistors. On the left and right I/O banks, some of the differential pin pairs (p and n
pins) of the true output drivers are not located on adjacent pins. In these cases, a
power pin is located between the p and n pins. These I/O standards are also
supported on all I/O banks using two single-ended output with the second output
programmed as inverted, and an external resistor network. True input buffers for
these I/O standards are supported on all I/O banks.
f For more information about the location of Cyclone III device family true differential
pins, refer to the Pin-Out Files for Altera Devices webpage on the Altera website.
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Cyclone III Device Handbook
Volume 1
December 2011
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