EP3C10U256C6N Datasheet, PDF (176/274 Pages) Altera Corporation – Cyclone III Device Family Overview

9–18
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
1 You can still use this method if the master and slave devices use the same .sof.
Figure 9–5. Multi-Device AS Configuration where the Devices Receive the Same Data with Multiple SRAM Object Files
V_CCIO (1) V_CCIO (1) V_CCIO (1) V_CCIO (2)
10 kΩ
10 kΩ
10 kΩ
10 kΩ
Slave Device of the Cyclone III Device Family
nSTATUS
CONF_DONE
nCONFIG
nCE
nCEO
N.C. (3)
Serial Configuration
Device
Master Device of the
Cyclone III Device
Family
nSTATUS
CONF_DONE
nCONFIG
nCE
nCEO
GND
DATA[0]
DCLK
MSEL[3..0]
(4)
Slave Device of the Cyclone III Device Family
nSTATUS
CONF_DONE
nCONFIG
nCE
nCEO
N.C. (3)
DATA
25 Ω (6)
DATA[0]
50 Ω (6),(8)
DCLK
DCLK
nCS
nCSO (5)
ASDI
ASDO (5)
MSEL[3..0]
(4)
DATA[0]
DCLK
MSEL[3..0]
(4)
50 Ω (8)
Slave Device of the Cyclone III Device Family
nSTATUS
CONF_DONE
nCONFIG
nCE
nCEO
N.C. (3)
Buffers (7)
DATA[0]
DCLK
MSEL[3..0]
(4)
Notes to Figure 9–5:
(1) Connect the pull-up resistors to the V_CCIO supply of the bank in which the pin resides.
(2) Connect the pull-up resistor to the V_CCIO supply voltage of the I/O bank in which the nCE pin resides.
(3) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.
(4) The MSEL pin settings vary for different configuration voltage standards and POR time. You must set the master device in AS mode and the slave
devices in PS mode. To connect MSEL[3..0] for the master device in AS mode and the slave devices in PS mode, refer to Table 9–7 on page 9–11.
Connect the MSEL pins directly to V_CCA or GND.
(5) These are dual-purpose I/O pins. The nCSO pin functions as the FLASH_NCE pin in AP mode. The ASDO pin functions as the DATA[1] pin in other
AP and FPP modes.
(6) Connect the series resistor at the near end of the serial configuration device.
(7) Connect the repeater buffers between the master and slave devices for DATA[0] and DCLK. All I/O inputs must maintain a maximum AC voltage
of 4.1 V. The output resistance of the repeater buffers must fit the maximum overshoot equation outlined in “Configuration and JTAG Pin I/O
Requirements” on page 9–7.
(8) The 50- series resistors are optional if the 3.3-V configuration voltage standard is applied. For optimal signal integrity, connect these 50- series
resistors if the 2.5- or 3.0-V configuration voltage standard is applied.
Cyclone III Device Handbook
Volume 1
August 2012 Altera Corporation