EP3C10U256C6N Datasheet, PDF (188/274 Pages) Altera Corporation – Cyclone III Device Family Overview

9–30
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
As shown in Figure 9–9 and Figure 9–10, the nSTATUS and CONF_DONE pins on all target
devices are connected together with external pull-up resistors. These pins are open-
drain bidirectional pins on the devices. When the first device asserts nCEO (after
receiving all its configuration data), it releases its CONF_DONE pin. However, the
subsequent devices in the chain keep this shared CONF_DONE line low until they receive
their configuration data. When all target devices in the chain receive their
configuration data and release CONF_DONE, the pull-up resistor drives a high level on
this line and all devices simultaneously enter initialization mode.
Guidelines for Connecting Parallel Flash to Cyclone III Devices for the AP
Interface
For the single- and multi-device AP configuration, the board trace length and loading
between the supported parallel flash and Cyclone III devices must follow the
recommendations listed in Table 9–12. These recommendations also apply to an AP
configuration with multiple bus masters.
Table 9–12. Maximum Trace Length and Loading for the AP Configuration
Cyclone III AP Pins
Maximum Board Trace Length from the
Cyclone III Device to the Flash Device
(Inches)
Maximum Board Load (pF)
DCLK
6
15
DATA[15..0]
6
30
PADD[23..0]
6
30
nRESET
6
30
Flash_nCE
6
30
nOE
6
30
nAVD
6
30
nWE
I/O ⁽¹⁾
6
30
6
30
Note to Table 9–12:
(1) The AP configuration ignores the WAIT signal from the flash during configuration mode. However, if you are
accessing flash during user mode with user logic, you can optionally use the normal I/O to monitor the WAIT signal
from the Micron P30 or P33 flash.
Configuring With Multiple Bus Masters
Similar to the AS configuration scheme, the AP configuration scheme supports
multiple bus masters for the parallel flash. For another master to take control of the
AP configuration bus, the master must assert nCONFIG low for at least 500 ns to reset
the master Cyclone III device and override the weak 10 k pull-down resistor on the
nCE pin. This resets the master Cyclone III device and causes it to tri-state its AP
configuration bus. The other master then takes control of the AP configuration bus.
After the other master is done, it releases the AP configuration bus, then releases the
nCE pin, and finally pulses nCONFIG low to restart the configuration.
In the AP configuration scheme, multiple masters share the parallel flash. Similar to
the AS configuration scheme, the bus control is negotiated by the nCE pin.
Cyclone III Device Handbook
Volume 1
August 2012 Altera Corporation