EP3C10U256C6N Datasheet, PDF (209/274 Pages) Altera Corporation – Cyclone III Device Family Overview

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
9–51
Figure 9–25. JTAG Configuration of a Single Device Using a Download Cable (1.5-V or 1.8-V V_CCIO
Powering the JTAG Pins)
V_CCIO
V_CCIO (2)
(1)
V_CCIO (2) 10 kΩ
10 kΩ
GND
N.C. (4)
(5)
(5)
(5)
(5)
Cyclone III Device Family
nCE (3)
TCK
TDO
nCEO
nSTATUS
CONF_DONE
nCONFIG
MSEL[3..0]
DATA[0]
DCLK
TMS
TDI
V_CCIO
(1)
Download Cable
10-Pin Male Header (Top View)
Pin 1
V_CCIO (6)
GND
V_IO (7)
1 kΩ
GND
GND
Notes to Figure 9–25:
(1) The resistor value can vary from 1 k to 10 k. Perform signal integrity analysis to select the resistor value for your
setup.
(2) Connect these pull-up resistors to the V_CCIO supply of the bank in which the pin resides.
(3) The nCE must be connected to GND or driven low for successful JTAG configuration.
(4) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.
(5) Connect the nCONFIG and MSEL[3..0] pins to support a non-JTAG configuration scheme. If you only use a JTAG
configuration, connect the nCONFIG pin to logic-high and the MSEL[3..0] pins to ground. In addition, pull DCLK and
DATA[0] either high or low, whichever is convenient on your board.
(6) Power up the V_CC of the ByteBlaster II, USB-Blaster, or Ethernet Blaster cable with supply from V_CCIO. The
ByteBlaster II, USB-Blaster, and Ethernet Blaster cables do not support a target supply voltage of 1.2 V. For the target
supply voltage value, refer to the ByteBlaster II Download Cable User Guide, USB-Blaster Download Cable User Guide
and Ethernet Blaster Communications Cable User Guide.
(7) In the USB-Blaster and ByteBlaster II cables, this pin is connected to nCE when it is used for AS programming;
otherwise it is a no connect.
To configure a single device in a JTAG chain, the programming software places all
other devices in bypass mode. In bypass mode, devices pass programming data from
the TDI pin to the TDO pin through a single bypass register without being affected
internally. This scheme enables the programming software to program or verify the
target device. Configuration data driven into the device appears on the TDO pin one
clock cycle later.
The Quartus II software verifies successful JTAG configuration upon completion. At
the end of configuration, the software checks the state of CONF_DONE through the JTAG
port. When the Quartus II software generates a .jam for a multi-device chain, it
contains instructions to have all devices in the chain initialize at the same time. If
CONF_DONE is not high, the Quartus II software indicates that configuration has failed.
If CONF_DONE is high, the software indicates that configuration was successful. After
the configuration bitstream is serially sent using the JTAG TDI port, the TCK port
clocks an additional clock cycle to perform device initialization.
August 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1