EP3C10U256C6N Datasheet, PDF (38/274 Pages) Altera Corporation – Cyclone III Device Family Overview

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Chapter 3: Memory Blocks in the Cyclone III Device Family
Overview
Byte Enable Support
The Cyclone III device family M9K memory blocks support byte enables that mask
the input data so that only specific bytes of data are written. The unwritten bytes
retain the previous written value. The wren signals, along with the byte-enable
(byteena) signals, control the write operations of the RAM block. The default value of
the byteena signals is high (enabled), in which case writing is controlled only by the
wren signals. There is no clear port to the byteena registers. M9K blocks support byte
enables when the write port has a data width of ×16, ×18, ×32, or ×36 bits.
Byte enables operate in one-hot manner, with the LSB of the byteena signal
corresponding to the least significant byte of the data bus. For example, if
byteena = 01 and you are using a RAM block in ×18 mode, data[8..0] is enabled
and data[17..9] is disabled. Similarly, if byteena = 11, both data[8..0] and
data[17..9] are enabled. Byte enables are active high.
Table 3–2 lists the byte selection.
Table 3–2. byteena for Cyclone III Device Family M9K Blocks ⁽¹⁾
byteena[3..0]
datain × 16
Affected Bytes
datain × 18
datain × 32
[0] = 1
[7..0]
[8..0]
[7..0]
[1] = 1
[15..8]
[17..9]
[15..8]
[2] = 1
—
—
[23..16]
[3] = 1
—
—
[31..24]
Note to Table 3–2:
(1) Any combination of byte enables is possible.
datain × 36
[8..0]
[17..9]
[26..18]
[35..27]
Figure 3–2 shows how the wren and byteena signals control the RAM operations.
Figure 3–2. Cyclone III Device Family byteena Functional Waveform ⁽¹⁾
inclock
wren
rden
address
an
a0
a1
a2
a0
data XXXX
ABCD
a1
a2
XXXX
byteena ^XX
10
01
11
XX
contents at a0
FFFF
ABFF
contents at a1
contents at a2
q (asynch)
FFFF
FFFF
doutn
ABFF
FFCD
ABCD
FFCD
ABCD
ABFF
FFCD
ABCD
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation