EP3C10U256C6N Datasheet, PDF (142/274 Pages) Altera Corporation – Cyclone III Device Family Overview

7–20
Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
Document Revision History
Table 7–6. Document Revision History (Part 2 of 2)
Date
May 2008
July 2007
March 2007
Version
Changes
Changes include addition of BLVD information
■ Updated “Introduction” section with BLVDS information.
■ Updated Figure 7–1 with BLVDS information and added Note 5.
■ Updated Table 7–1 and added BLVDS information.
■ Updated “Cyclone III High-Speed I/O Banks” section with BLVDS information.
■ Updated Table 7–2 and 7–6.
■ Added new section “BLVDS I/O Standard Support in Cyclone III Devices”.
1.2 ■ Updated Note 4 to Figure 7–4.
■ Updated Note 1 to Figure 7–10.
■ Updated Note 1 to Figure 7–11.
■ Updated Note 1 to Figure 7–14.
■ Updated “Mini-LVDS I/O Standard Support in Cyclone III Devices” section.
■ Updated Note 1 to Figure 7–17.
■ Updated “LVPECL I/O Support in Cyclone III Devices” section.
■ Added new Figure 7–18.
■ Added note that PLL output clock pins do not support Class II type of selected differential
I/O standards.
■ Added Table 8–3 that lists the number of differential channels which are migratable
across densities and packages.
■ Updated (Note 4) to Figure 7–1.
1.1 _{■ Updated (Note 3) to Table 7–1.}
■ Added new Table 7–3.
■ Added (Note 1) to Figure 7–21.
■ Added (Note 1) to Figure 7–23.
■ Added chapter TOC and “Referenced Documents” section.
1.0 Initial release.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation