AK4642EN Datasheet, PDF (80/83 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP/SPK-AMP

ASAHI KASEI
[AK4642EN]
3. PLL Slave (MCKI pin)
PMPLL bit
(Addr:01H, D0)
MCKO bit
(Addr:01H, D1)
External MCKI
(1)
(1)
(2)
Input
Example
Audio I/F Format: MSB justified (ADC & DAC)
PLL Reference clock: MCKI
BICK frequency: 64fs
Sampling Frequency: 8kHz
(1) Addr:01H, Data:00H
(2) Stop the external clocks
Figure 58. Clock Stopping Sequence (3)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
Stop MCKO output: MCKO bit = “1” → “0”
(2) Stop the external master clock.
4. EXT Slave Mode
External MCKI
External BICK
External LRCK
Input
Input
Input
(1)
Example
(1)
Audio I/F Format :MSB justified(ADC & DAC)
Input MCKI frequency:1024fs
Sampling Frequency:8kHz
(1)
(1) Stop the external clocks
Figure 59. Clock Stopping Sequence (4)
<Example>
(1) Stop the external MCKI, BICK and LRCK clocks.
„ Power down
Power supply current can be shut down (typ. 10µA) by stopping clocks and setting PMVCM bit = “0” after all blocks
except for VCOM are powered-down. Power supply current can be also shut down (typ. 10µA) by stopping clocks and
setting PDN pin = “L”. When PDN pin = “L”, the registers are initialized.
MS0420-E-00
- 80 -
2005/09