AK4642EN Datasheet, PDF (18/83 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP/SPK-AMP

ASAHI KASEI
„ Timing Diagram
MCKI
LRCK
MCKO
[AK4642EN]
1/fCLK
VIH
VIL
tCLKH
tCLKL
1/fs
tLRCKH
tLRCKL
1/fMCK
50%DVDD
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
tMCKL
50%DVDD
dMCK = tMCKL x fMCK x 100
Figure 3. Clock Timing (PLL Master mode)
LRCK
BICK
SDTO
SDTI
50%DVDD
tBLR
tDLR
tBCKL
tBSD
50%DVDD
50%DVDD
tSDS
tSDH
VIH
VIL
Figure 4. Audio Interface Timing (PLL Master mode)
MS0420-E-00
- 18 -
2005/09