AK4642EN Datasheet, PDF (60/83 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP/SPK-AMP

ASAHI KASEI
[AK4642EN]
Addr
03H
Register Name
Signal Select 2
Default
D7
D6
D5
D4
D3
D2
D1
D0
LOVL LOPS MGAIN1 SPKG1 SPKG0 BEEPL
0
0
0
0
0
0
0
0
0
0
BEEPL: Switch Control from MIN pin to Stereo Line Output
0: OFF (Default)
1: ON
When PMLO bit is “1”, BEEPL bit is enabled. When PMLO bit is “0”, the LOUT/ROUT pins go to AVSS.
SPKG1-0: Speaker-Amp Output Gain Select (See Table 41)
MGAIN1: MIC-Amp Gain Control (See Table 16)
LOPS: Stereo Line Output Power-Save Mode
0: Normal Operation (Default)
1: Power-Save Mode
LOVL: Stereo Line Output Gain Select (Table 37)
0: 0dB (Default)
1: +2dB
Addr
04H
Register Name
Mode Control 1
Default
D7
D6
D5
D4
D3
D2
PLL3 PLL2 PLL1 PLL0 BCKO
0
0
0
0
0
0
0
DIF1-0: Audio Interface Format (See Table 13)
Default: “10” (Left jutified)
BCKO: BICK Output Frequency Select at Master Mode (See Table 10)
PLL3-0: PLL Reference Clock Select (See Table 4)
Default: “0000”(LRCK pin)
D1
DIF1
1
D0
DIF0
0
Addr
05H
Register Name
Mode Control 2
Default
D7
D6
D5
D4
D3
D2
D1
D0
PS1
PS0
FS3
0
0
FS2
FS1
FS0
0
0
0
0
0
0
0
0
FS3-0: Sampling Frequency Select (See Table 5 and Table 6.) and MCKI Frequency Select (See Table 11.)
FS3-0 bits select sampling frequency at PLL mode and MCKI frequency at EXT mode.
PS1-0: MCKO Output Frequency Select (Table 9)
Default: “00”(256fs)
MS0420-E-00
- 60 -
2005/09