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AK4642EN Datasheet, PDF (12/83 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP/SPK-AMP | |||
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ASAHI KASEI
[AK4642EN]
Parameter
min
typ
max
Units
Speaker-Amp Characteristics: DAC â SPP/SPN pins, ALC=OFF, IVOL=0dB, DVOL=0dB, RL=8â¦, BTL,
HVDD=3.3V
Output Voltage (Note 21)
SPKG1-0 bits = â00â, â0.5dBFS (Po=150mW)
-
3.11
-
Vpp
SPKG1-0 bits = â01â, â0.5dBFS (Po=240mW)
3.13
3.92
4.71
Vpp
SPKG1-0 bits = â10â, â2.5dBFS (Po=400mW)
-
1.79
-
Vrms
S/(N+D)
SPKG1-0 bits = â00â, â0.5dBFS (Po=150mW)
-
60
-
dB
SPKG1-0 bits = â01â, â0.5dBFS (Po=240mW)
20
50
-
dB
SPKG1-0 bits = â10â, â2.5dBFS (Po=400mW)
-
20
-
dB
S/N
(A-weighted)
80
90
-
dB
Load Resistance
8
-
-
â¦
Load Capacitance
-
-
30
pF
Speaker-Amp Characteristics: DAC â SPP/SPN pins, ALC=OFF, IVOL=0dB, DVOL=0dB, CL=3µF, Rserial=10⦠x 2,
RL=50â¦, BTL, HVDD=5.0V
Output Voltage SPKG1-0 bits = â10â, 0dBFS
-
6.75
-
Vpp
(Note 21) SPKG1-0 bits = â11â, 0dBFS
6.80
8.50
10.20
Vpp
S/(N+D)
SPKG1-0 bits = â10â, 0dBFS
-
60
-
dB
(Note 22) SPKG1-0 bits = â11â, 0dBFS
40
50
-
dB
S/N
(A-weighted)
80
90
-
dB
Load Resistance (Note 23)
50
-
-
â¦
Load Capacitance (Note 23)
-
-
3
µF
Mono Input: MIN pin (External Input Resistance=20kâ¦)
Maximum Input Voltage (Note 24)
-
1.98
-
Vpp
Gain (Note 25)
MIN Ã LOUT/ROUT LOVL bit = â0â
â4.5
0
+4.5
dB
LOVL bit = â1â
-
+2
-
dB
MIN Ã HPL/HPR
HPG bit = â0â
â24.5
â20
â15.5
dB
HPG bit = â1â
-
â16.4
-
dB
MIN Ã SPP/SPN
ALC bit = â0â, SPKG1-0 bits = â00â
â0.57
+4.43
+8.93
dB
ALC bit = â0â, SPKG1-0 bits = â01â
-
+6.43
-
dB
ALC bit = â0â, SPKG1-0 bits = â10â
-
+10.65
-
dB
ALC bit = â0â, SPKG1-0 bits = â11â
-
+12.65
-
dB
ALC bit = â1â, SPKG1-0 bits = â00â
-
+6.43
-
dB
ALC bit = â1â, SPKG1-0 bits = â01â
-
+8.43
-
dB
ALC bit = â1â, SPKG1-0 bits = â10â
-
+12.65
-
dB
ALC bit = â1â, SPKG1-0 bits = â11â
-
+14.65
-
dB
Note 21. Output voltage is proportional to AVDD voltage.
Vout = 0.94 x AVDD(typ)@SPKG1-0 bits = â00â, 1.19 x AVDD(typ)@SPKG1-0 bits = â01â, 2.05 x
AVDD(typ)@SPKG1-0 bits = â10â, 2.58 x AVDD(typ)@SPKG1-0 bits = â11â at Full-differential output.
Note 22. In case of measuring at SPP and SPN pins.
Note 23. Load impedance is total impedance of series resistance and piezo speaker impedance at 1kHz in Figure 33. Load
capacitance is capacitance of piezo speaker. When piezo speaker is used, 10⦠or more series resistors should be
connected at both SPP and SPN pins, respectively.
Note 24. Maximum voltage is in proportion to both AVDD and external input resistance (Rin). Vin = 0.6 x AVDD x Rin
/ 20k⦠(typ).
Note 25. The gain is in inverse proportion to external input resistance.
MS0420-E-00
- 12 -
2005/09
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