AK4642EN Datasheet, PDF (49/83 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP/SPK-AMP

ASAHI KASEI
[AK4642EN]
„ Speaker Output
Power supply for Speaker-Amp (HVDD) is 2.6V to 5.25V. In case of dynamic (electromagnetic) speaker (load resistance
< 50Ω), HVDD is 2.6V to 3.6V.
Speaker Type
Dynamic Speaker
Piezo (Ceramic) Speaker
HVDD
2.6 ∼ 3.6V
2.6 ∼ 5.25V
Load Resistance (min)
8Ω
50Ω (Note 23)
Load Capacitance (max)
30pF
3µF (Note 23)
Note 23. Load impedance is total impedance of series resistance and piezo speaker impedance at 1kHz in Figure 33. Load
capacitance is capacitance of piezo speaker. When piezo speaker is used, 10Ω or more series resistors should be
connected at both SPP and SPN pins, respectively.
Table 40. Speaker Type and Power Supply Range
The DAC output signal is input to the Speaker-amp as [(L+R)/2]. The Speaker-amp is mono and BTL output. The gain is
set by SPKG1-0 bits. Output level depends on AVDD voltage and SPKG1-0 bits.
SPKG1-0 bits
00
01
10
11
Gain
ALC bit = “0”
ALC bit = “1”
+4.43dB
+6.43dB
+6.43dB
+8.43dB
+10.65dB
+12.65dB
+12.65dB
+14.65dB
Table 41. SPK-Amp Gain
Default
AVDD HVDD SPKG1-0 bits
SPK-Amp Output (DAC Input = 0dBFS)
ALC bit = “0”
ALC bit = “1”
(LMTH1-0 bits = “00”)
00
3.30Vpp
3.11Vpp
3.3V
01
4.15Vpp (Note 40)
3.92Vpp
10
6.75Vpp (Note 40)
6.37Vpp (Note 40)
3.3V
11
8.50Vpp (Note 40)
8.02Vpp (Note 40)
00
3.30Vpp
3.11Vpp
5.0V
01
10
4.15Vpp
6.75Vpp
3.92Vpp
6.37Vpp
11
8.50Vpp
8.02Vpp
Note 40. The output level is calculated by assuming that output signal is not clipped. In actual case, output signal may be
clipped when DAC outputs 0dBFS signal. DAC output level should be set to lower level by setting digital
volume so that Speaker-Amp output level is 4.0Vpp or less and output signal is not clipped.
Table 42. SPK-Amp Output Level
MS0420-E-00
- 49 -
2005/09