AK4642EN Datasheet, PDF (29/83 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP/SPK-AMP

ASAHI KASEI
[AK4642EN]
„ System Reset
Upon power-up, the AK4642 should be reset by bringing the PDN pin = “L”. This ensures that all internal registers reset
to their initial values.
The ADC enters an initialization cycle that starts when the PMADL or PMADR bit is changed from “0” to “1” at PMDAC
bits is “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the ADC digital
data outputs of both channels are forced to a 2's compliment, “0”. The ADC output reflects the analog input signal after
the initialization cycle is complete. When PMDAC bit is “1”, the ADC does not require an initialization cycle.
The DAC enters an initialization cycle that starts when the PMDAC bit is changed from “0” to “1” at PMADL and
PMADR bits are “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the
DAC input digital data of both channels are internally forced to a 2's compliment, “0”. The DAC output reflects the digital
input data after the initialization cycle is complete. When PMADC or PMADR bit is “1”, the DAC does not require an
initialization cycle.
„ Audio Interface Format
Three types of data formats are available and are selected by setting the DIF1-0 bits (seeTable 13). In all modes, the serial
data is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. LRCK
and BICK are output from the AK4642 in master mode, but must be input to the AK4642 in slave mode. The SDTO is
clocked out on the falling edge (“↓”) of BICK and the SDTI is latched on the rising edge (“↑”).
Mode
0
1
2
3
DIF1 bit
0
0
1
1
DIF0 bit
0
1
0
1
SDTO (ADC) SDTI (DAC)
N/A
N/A
MSB justified LSB justified
MSB justified
I²S compatible
MSB justified
I²S compatible
Table 13. Audio Interface Format
BICK
N/A
≥ 32fs
≥ 32fs
≥ 32fs
Figure
-
Figure 17
Figure 18
Figure 19
Default
If 16-bit data that ADC outputs is converted to 8-bit data by removing LSB 8-bit, “−1” at 16bit data is converted to “−1”
at 8-bit data. And when the DAC playbacks this 8-bit data, “−1” at 8-bit data will be converted to “−256” at 16-bit data
and this is a large offset. This offset can be removed by adding the offset of “128” to 16-bit data before converting to 8-bit
data.
LRCK
0123
BICK(32fs)
SDTO(o)
15 14 13
9 10 11 12 13 14 15 0 1 2 3
7 6 5 4 3 2 1 0 15 14 13
9 10 11 12 13 14 15 0 1
7 6 5 4 3 2 1 0 15
SDTI(i)
15 14 13
0123
BICK(64fs)
SDTO(o)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
15 16 17 18
31 0 1 2 3
10
15 14 13
7 6 5 4 3 2 1 0 15
15 16 17 18
31 0 1
10
15
SDTI(i)
Don't Care
15:MSB, 0:LSB
15 14
Lch Data
10
Don't Care
15 14 2 1 0
Rch Data
Figure 17. Mode 1 Timing
MS0420-E-00
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2005/09