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AK4642EN Datasheet, PDF (77/83 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP/SPK-AMP | |||
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ASAHI KASEI
[AK4642EN]
 Headphone-amp Output
FS3-0 bits X,XXX
(Addr:05H, D5&D2-0)
DACH bit
(Addr:0FH, D0)
(1)
(2)
BST1-0 bits
(Addr:0EH, D3-2)
IVL/R7-0 bits
(Addr:09H&0CH, D7-0)
00
E1H
(3)
(4)
DVL/R7-0 bits
(Addr:0AH&0DH, D7-0)
PMDAC bit
(Addr:00H, D2)
18H
(5)
(6)
1,111
XX
91H
XXH
(13)
00
(12)
E x a m p le :
P LL M aster M ode
S a m p lin g F re q u e n c y: 4 4 .1 k H z
D V O L C b it = â1 â(d e fa u lt)
D ig ita l V o lu m e L e ve l: 0 dB
B a ss B o o st L e ve l: M id d le
D e-em phases response: O F F
S o ft M u te T im e : 2 5 6 /fs
(1 ) A d d r:0 5 H , D a ta :2 7 H
(2 ) A d d r:0 F H , D a ta 0 9 H
(3) A ddr:0E H , D ata 14 H
(4) A ddr:09H & 0C H , D ata 9 1H
(5 ) A d d r:0 A H & 0 D H , D a ta 2 8 H
(6) A ddr:00H , D ata 64H
(11)
(7) A ddr:01H , D ata 39H
(8) A ddr:01H , D ata 79H
PMBP bit
(Addr:00H, D5)
P la yb a c k
PMHPL/R bits
(Addr:01H, D5-4)
(7)
(10)
(9) A ddr:01H , D ata 39H
(1 0 ) A d d r:0 1 H , D a ta 0 9 H
HPMTN bit
(Addr:01H, D6)
(8)
(9)
(1 1 ) A d d r:0 0 H , D a ta 4 0 H
HPL/R pins
Normal Output
(1 2 ) A d d r:0 E H , D a ta 0 0 H
(1 3 ) A d d r:0 F H , D a ta 0 8 H
Figure 54. Headphone-Amp Output Sequence
<Example>
At first, clocks should be supplied according to âClock Set Upâ sequence.
(1) Set up a sampling frequency (FS3-0 bits).
(2) Set up the path of âDAC â HP-Ampâ: DACH bit = â0â â â1â
(3) Set up the low frequency boost level (BST1-0 bits)
(4) Set up the input digital volume (Addr: 09H and 0CH)
When PMADL = PMADR bits = â0â, IVL7-0 and IVR7-0 bits should be set to â91Hâ(0dB).
(5) Set up the output digital volume (Addr: 0AH and 0DH)
When DVOLC bit is â1â (default), DVL7-0 bits set the volume of both channels. After DAC is powered-up,
the digital volume changes from default value (0dB) to the register setting value by the soft transition.
(6) Power up DAC and MIN-Amp: PMDAC = PMBP bits = â0â â â1â
The DAC enters an initialization cycle that starts when the PMDAC bit is changed from â0â to â1â at PMADL
and PMADR bits are â0â. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the
initialization cycle, the DAC input digital data of both channels are internally forced to a 2's compliment, â0â.
The DAC output reflects the digital input data after the initialization cycle is complete. When PMADC or
PMADR bit is â1â, the DAC does not require an initialization cycle. When ALC bit is â1â, ALC is disable
(ALC gain is set by IVL/R7-0 bits) during an intialization cycle (1059/fs=24ms@fs=44.1kHz). After the
initialization cycle, ALC operation starts from the gain set by IVL/R7-0 bits.
(7) Power up headphone-amp: PMHPL = PMHPR bits = â0â â â1â
Output voltage of headphone-amp is still HVSS.
(8) Rise up the common voltage of headphone-amp: HPMTN bit = â0â â â1â
The rise time depends on HVDD and the capacitor value connected with the MUTET pin. When HVDD=3.3V
and the capacitor value is 1.0µF, the time constant is Ïr = 100ms(typ), 250ms(max).
(9) Fall down the common voltage of headphone-amp: HPMTN bit = â1â â â0â
The fall time depends on HVDD and the capacitor value connected with the MUTET pin. When HVDD=3.3V
and the capacitor value is 1.0µF, the time constant is Ï f = 100ms(typ), 250ms(max).
If the power supply is powered-off or headphone-Amp is powered-down before the common voltage goes to
GND, the pop noise occurs. It takes twice of Ïf that the common voltage goes to GND.
(10) Power down headphone-amp: PMHPL = PMHPR bits = â1â â â0â
(11) Power down DAC and MIN-Amp: PMDAC = PMBP bits = â1â â â0â
(12) Off the bass boost: BST1-0 bits = â00â
(13) Disable the path of âDAC â HP-Ampâ: DACH bit = â1â â â0â
MS0420-E-00
- 77 -
2005/09
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