AK4642EN Datasheet, PDF (24/83 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP/SPK-AMP

ASAHI KASEI
[AK4642EN]
„ PLL Mode
When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the
PLL3-0 and FS3-0 bits. The PLL lock time is shown in Table 4, whenever the AK4642 is supplied to a stable clocks after
PLL is powered-up (PMPLL bit = “0” → “1”) or sampling frequency changes.
1) Setting of PLL Mode
Mode
PLL3 PLL2
bit bit
0
0
0
1
0
0
2
0
0
3
0
0
4
0
1
5
0
1
6
0
1
7
0
1
12
1
1
13
1
1
Others
Others
PLL
PLL1 PLL0 Reference
Input
R and C of
VCOC pin
bit bit Clock Input
Pin
Frequency _{R[Ω] C[F]}
0
0
LRCK pin
1fs
6.8k 220n
0
1
N/A
-
-
-
1
0
BICK pin
32fs
10k 4.7n
10k 10n
1
1
BICK pin
64fs
10k 4.7n
10k 10n
0
0
MCKI pin 11.2896MHz 10k 4.7n
0
1
MCKI pin
12.288MHz 10k 4.7n
1
0
MCKI pin
12MHz
10k 4.7n
1
1
MCKI pin
24MHz
10k 4.7n
0
0
MCKI pin
13.5MHz
10k 10n
0
1
MCKI pin
27MHz
10k 10n
N/A
Table 4. Setting of PLL Mode (*fs: Sampling Frequency)
PLL Lock
Time
(max)
160ms
-
2ms
4ms
2ms
4ms
40ms
40ms
40ms
40ms
40ms
40ms
Default
2) Setting of sampling frequency in PLL Mode
When PLL2 bit is “1” (PLL reference clock input is MCKI pin), the sampling frequency is selected by FS3-0 bits as
defined in Table 5.
Mode
FS3 bit
FS2 bit
FS1 bit
FS0 bit Sampling Frequency
0
0
0
0
0
8kHz
Default
1
0
0
0
1
12kHz
2
0
0
1
0
16kHz
3
0
0
1
1
24kHz
4
0
1
0
0
7.35kHz
5
0
1
0
1
11.025kHz
6
0
1
1
0
14.7kHz
7
0
1
1
1
22.05kHz
10
1
0
1
0
32kHz
11
1
0
1
1
48kHz
14
1
1
1
0
29.4kHz
15
1
1
1
1
44.1kHz
Others
Others
N/A
Table 5. Setting of Sampling Frequency at PLL2 bit = “1” and PMPLL bit = “1”
When PLL2 bit is “0” (PLL reference clock input is LRCK or BICK pin), the sampling frequency is selected by FS3 and
FS1-0 bits. (See Table 6). FS2 bit is “don’t care”.
Mode FS3 bit FS2 bit FS1 bit FS0 bit Sampling Frequency Range
0
0
Don’t care
0
0
7.35kHz ≤ fs ≤ 8kHz Default
1
0
Don’t care
0
1
8kHz < fs ≤ 12kHz
2
0
Don’t care
1
0
12kHz < fs ≤ 16kHz
3
0
Don’t care
1
1
16kHz < fs ≤ 24kHz
6
1
Don’t care
1
0
24kHz < fs ≤ 32kHz
7
1
Don’t care
1
1
32kHz < fs ≤ 48kHz
Others
Others
N/A
Table 6. Setting of Sampling Frequency at PLL2 bit = “0” and PMPLL bit = “1”
MS0420-E-00
- 24 -
2005/09