AK4642EN Datasheet, PDF (16/83 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP/SPK-AMP

ASAHI KASEI
[AK4642EN]
Parameter
Symbol
min
PLL Slave Mode (PLL Reference Clock = LRCK pin)
LRCK Input Timing
Frequency
fs
7.35
Duty
Duty
45
BICK Input Timing
Period
tBCK
1/(64fs)
Pulse Width Low
tBCKL
240
Pulse Width High
tBCKH
240
PLL Slave Mode (PLL Reference Clock = BICK pin)
LRCK Input Timing
Frequency
fs
7.35
Duty
Duty
45
BICK Input Timing
Period
PLL3-0 bits = “0010”
tBCK
-
PLL3-0 bits = “0011”
tBCK
-
Pulse Width Low
tBCKL 0.4 x tBCK
Pulse Width High
tBCKH 0.4 x tBCK
External Slave Mode
MCKI Input Timing
Frequency 256fs
fCLK
1.8816
512fs
fCLK
3.7632
1024fs
fCLK
7.5264
Pulse Width Low
tCLKL 0.4/fCLK
Pulse Width High
tCLKH 0.4/fCLK
LRCK Input Timing
Frequency 256fs
fs
7.35
512fs
fs
7.35
1024fs
fs
7.35
Duty
Duty
45
BICK Input Timing
Period
tBCK
312.5
Pulse Width Low
tBCKL
130
Pulse Width High
tBCKH
130
Audio Interface Timing
Master Mode
BICK “↓” to LRCK Edge (Note 34)
tMBLR
−40
LRCK Edge to SDTO (MSB)
(Except I²S mode)
tLRD
−70
BICK “↓” to SDTO
tBSD
−70
SDTI Hold Time
tSDH
50
SDTI Setup Time
tSDS
50
Slave Mode
LRCK Edge to BICK “↑” (Note 34)
tLRB
50
BICK “↑” to LRCK Edge (Note 34)
tBLR
50
LRCK Edge to SDTO (MSB)
(Except I²S mode)
tLRD
-
BICK “↓” to SDTO
SDTI Hold Time
tBSD
-
tSDH
50
SDTI Setup Time
tSDS
50
Note 34. BICK rising edge must not occur at the same time as LRCK edge.
typ
-
-
-
-
-
-
-
1/(32fs)
1/(64fs)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
max
Units
48
kHz
55
%
1/(32fs)
ns
-
ns
-
ns
48
kHz
55
%
-
ns
-
ns
-
ns
-
ns
12.288
13.312
13.312
-
-
48
26
13
55
-
-
-
MHz
MHz
MHz
ns
ns
kHz
kHz
kHz
%
ns
ns
ns
40
ns
70
ns
70
ns
-
ns
-
ns
-
ns
-
ns
80
ns
80
ns
-
ns
-
ns
MS0420-E-00
- 16 -
2005/09