|
AK4642EN Datasheet, PDF (75/83 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP/SPK-AMP | |||
|
◁ |
ASAHI KASEI
[AK4642EN]
 Speaker-amp Output
FS3-0 bits X,XXX
(Addr:05H, D5&D2-0)
(1)
DACS bit
(Addr:02H, D3)
(2)
SPKG1-0 bits
(Addr:03H, D4-3)
ALC Control 1
(Addr:06H)
ALC Control 2
(Addr:08H)
00
XXH
XXH
(3)
(4)
(5)
1,111
01
3CH
C1H
Example:
PLL Master Mode
(13)
Audio I/F Format: MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
Digital Volume: 0dB
ALC: Enable
(1) Addr:05H, Data:27H
(2) Addr:02H, Data:20H
(3) Addr:03H, Data:08H
(4) Addr:06H, Data:3CH
ALC Control 3
(Addr:0BH)
ALC bit
(Addr:07H, D5)
IVL/R7-0 bits
(Addr:09H&0CH, D7-0)
DVL/R7-0 bits
(Addr:0AH&0DH, D7-0)
PMDAC bit
(Addr:00H, D2)
PMBP bit
(Addr:00H, D5)
PMSPK bit
(Addr:00H, D4)
SPPSN bit
(Addr:02H, D7)
SPP pin
XXH
0
E1H
18H
(6)
(7)
00H
X
91H
(8)
XXH
(9)
(14)
(10)
Hi-Z
(11)
(12)
Normal Output
Hi-Z
(5) Addr:08H, Data:E1H
(6) Addr:0BH, Data:00H
(7) Addr:07H, Data:20H
(8) Addr:09H & 0CH, Data:91H
(9) Addr:0AH & 0DH, Data:28H
(10) Addr:00H, Data:74H
(11) Addr:02H, Data:A0H
Playback
(12) Addr:02H, Data:20H
(13) Addr:02H, Data:00H
SPN pin
Hi-Z
HVDD/2 Normal Output HVDD/2 Hi-Z
(14) Addr:00H, Data:40H
Figure 52. Speaker-Amp Output Sequence
<Example>
At first, clocks should be supplied according to âClock Set Upâ sequence.
(1) Set up a sampling frequency (FS3-0 bits). When the AK4642 is PLL mode, DAC and Speaker-Amp should be
powered-up in consideration of PLL lock time after a sampling frequency is changed.
(2) Set up the path of âDAC Ã SPK-Ampâ: DACS bit = â0â Ã â1â
(3) SPK-Amp gain setting: SPKG1-0 bits = â00â Ã â01â
(4) Set up Timer Select for ALC (Addr: 06H)
(5) Set up REF value for ALC (Addr: 08H)
(6) Set up LMTH1 and RGAIN1 bits (Addr: 0BH)
(7) Set up LMTH0, RGAIN0, LMAT1-0 and ALC bits (Addr: 07H)
When PMADL or PMADR bit is â1â, ALC for DAC path is disabled.
(8) Set up the input digital volume (Addr: 09H and 0CH)
When PMADL = PMADR bits = â0â, IVL7-0 and IVR7-0 bits should be set to â91Hâ(0dB).
(9) Set up the output digital volume (Addr: 0AH and 0DH).
When DVOLC bit is â1â (default), DVL7-0 bits set the volume of both channels. After DAC is powered-up, the
digital volume changes from default value (0dB) to the register setting value by the soft transition.
(10) Power Up of DAC, MIN-Amp and Speaker-Amp: PMDAC = PMBP = PMSPK bits = â0â â â1â
The DAC enters an initialization cycle that starts when the PMDAC bit is changed from â0â to â1â at PMADL
and PMADR bits are â0â. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization
cycle, the DAC input digital data of both channels are internally forced to a 2's compliment, â0â. The DAC
output reflects the digital input data after the initialization cycle is complete. When PMADC or PMADR bit is
â1â, the DAC does not require an initialization cycle. When ALC bit is â1â, ALC is disable (ALC gain is set by
IVL/R7-0 bits) during an intialization cycle (1059/fs=24ms@fs=44.1kHz). After the initialization cycle, ALC
operation starts from the gain set by IVL/R7-0 bits.
(11) Exit the power-save-mode of Speaker-Amp: SPPSN bit = â0â â â1â
(12) Enter the power-save-mode of Speaker-Amp: SPPSN bit = â1â â â0â
(13) Disable the path of âDAC Ã SPK-Ampâ: DACS bit = â1â Ã â0â
(14) Power Down DAC, MIN-Amp and Speaker-Amp: PMDAC = PMBP = PMSPK bits = â1â â â0â
MS0420-E-00
- 75 -
2005/09
|
▷ |