AK4642EN Datasheet, PDF (26/83 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP/SPK-AMP

ASAHI KASEI
[AK4642EN]
„ PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13.5MHz, 24MHz or 27MHz) is input to MCKI pin, the
MCKO, BICK and LRCK clocks are generated by an internal PLL circuit. The MCKO output frequency is selected by
PS1-0 bits (see Table 9) and the output is enabled by MCKO bit. The BICK output frequency is selected between 32fs or
64fs, by BCKO bit (see Table 10).
AK4642
11.2896MHz, 12MHz, 12.288MHz
13.5MHz, 24MHz, 27MHz
DSP or µP
MCKI
MCKO
BICK
LRCK
SDTO
SDTI
256fs/128fs/64fs/32fs
32fs, 64fs
1fs
MCLK
BCLK
LRCK
SDTI
SDTO
Figure 13. PLL Master Mode
Mode
PS1 bit
PS0 bit
MCKO pin
0
0
0
256fs
Default
1
0
1
128fs
2
1
0
64fs
3
1
1
32fs
Table 9. MCKO Output Frequency (PLL Mode, MCKO bit = “1”)
BCKO bit
BICK Output
Frequency
0
32fs
Default
1
64fs
Table 10. BICK Output Frequency at Master Mode
MS0420-E-00
- 26 -
2005/09