AK4137EQ Datasheet, PDF (52/65 Pages) Asahi Kasei Microsystems – 32bit SRC with PCM/DSD conversion

[AK4137]
READ Operation
Set the R/W bit = “1” for the READ operation of the AK4137. After transmission of data, the master
can read the next address’s data by generating an acknowledge instead of terminating the write
cycle after the receipt of the first data word. After receiving each data packet the internal 6-bit address
counter is incremented by one, and the next data is automatically taken into the next address. If the
address exceeds 06H prior to generating stop condition, the address counter will “roll over” to 00H
and the data of 00H will be read out.
The AK4137 supports two basic read operations: Current Address Read and Random Address Read.
1. Current Address Read
The AK4137 contains an internal address counter that maintains the address of the last word
accessed, incremented by one. Therefore, if the last access (either a read or write) was to address
“n”, the next CURRENT READ operation would access data from the address “n+1”. After receipt of
the slave address with R/W bit “1”, the AK4137 generates an acknowledge, transmits 1-byte of data
to the address set by the internal address counter and increments the internal address counter by 1.
If the master does not generate an acknowledge but generates a stop condition instead, the AK4137
discontinues transmission.
S
T
A
R/W="1"
R
T
SDA
S lave
S _Address
A
C
K
Data(n)
Data(n+1)
Data(n+2)
A
A
A
C
C
C
K
K
K
Figure 50. Current Address Read
Data(n+x)
A
C
K
S
T
O
P
P
A
C
K
2. Random Address Read
The random read operation allows the master to access any memory location at random. Prior to
issuing a slave address with the R/W bit =“1”, the master must execute a “dummy” write operation
first. The master issues a start request, a slave address (R/W bit = “0”) and then the register address
to read. After the register address is acknowledged, the master immediately reissues the start request
and the slave address with the R/W bit =“1”. The AK4137 then generates an acknowledge, 1 byte of
data and increments the internal address counter by 1. If the master does not generate an
acknowledge but generates a stop condition instead, the AK4137 discontinues transmission.
S
T
A
R/W="0"
R
T
S
T
A
R/W="1"
R
T
SDA
S lave
S _Address
S ub
A ddress(n)
S lave
S _Address
Data(n)
Data(n+1)
A
A
A
A
A
C
C
C
C
C
K
K
K
K
K
Figure 51. Random Address Read
S
T
O
P
Data(n+x)
P
A
A
C
C
K
K
Rev. 0.2
- 52 -
2014/06