AK4137EQ Datasheet, PDF (48/65 Pages) Asahi Kasei Microsystems – 32bit SRC with PCM/DSD conversion

[AK4137]
1. When the frequency of ILRCK at input port is changed without a reset by the PDN pin or RSTN bit.
When the difference of internal oscillator clock (min. 59.4 MHz, typ. 73.5 MHz) number in one
ILRCK cycle between before ILRCK frequency is changed (FSO/FSI ratio is stabilized) and after
the change is more than ±100 for 8cycles, an internal reset is made automatically and sampling
frequency ratio detection is executed again. SDTO outputs “L” when the internal reset is made,
and SRC data is output after “0.5/FSI+8/FSI(O)+156/FSO” or “1.5/FSI+8/FSI(O)+156/FSO”
(FSI(O) is lower frequency between FSI and FSO).
If the difference of internal oscillator clock number in one ILRCK cycle between before ILRCK
frequency is changed and after the change is less than ±100 or more than ±100 but shorter than
8cycles, the internal reset is not executed. In both cases; when ILRCK frequency is changed
immediately without transition time or with transition time which is not long enough for an internal
reset, it takes 5148/FSO (max. 643.5ms @FSO=8kHz) (Note 32) to output normal SRC data.
Distorted data may be output until normal SRC output.
When ILRCKx is stopped, an internal reset is executed automatically. It takes
“0.5/FSI+8/FSI(O)+156/FSO” or “1.5/FSI+8/FSI(O)+156/FSO” [s] to output normal SRC data after
ILRCKx is input again (FSI(O) is lower frequency between FSI and FSO).
2. When the frequency of OLRCK at output port is changed without a reset by the PDN pin or RSTN bit.
When the difference of internal oscillator clock number in one OLRCK cycle between before
OLRCK frequency is changed (FSO/FSI ratio is stabilized) and after the change is more than ±100
for 8cycles, an internal reset is made automatically and sampling frequency ratio detection is
executed again. SDTO outputs “L” when the internal reset is made, and SRC data is output after
“0.5/FSI+8/FSI(O)+156/FSO” or “1.5/FSI+8/FSI(O) +156/FSO” (FSI(O) is lower frequency between
FSI and FSO).
If the difference of internal oscillator clock number in one OLRCK cycle between before an OLRCK
frequency change and after the change is less than ±100 or more than ±100 but shorter than
8cycles, the internal reset is not executed. It takes 5148/FSO (max. 643.5ms @FSO=8kHz) (Note
32) to output normal SRC data. Distorted data may be output until normal SRC output.
When OLRCK is stopped, an internal reset is executed automatically. It takes
“0.5/FSI+8/FSI(O)+156/FSO” or “1.5/FSI+8/FSI(O)+156/FSO” [s] to output normal SRC data after
ILRCKx is input again (FSI(O) is lower frequency between FSI and FSO).
Note 32. When FSO=8kHz and FSO/FSI ratio is changed from 1/6 to 1/5.99. It is 160.9ms when
FSO=32kHz and FSO/fSI ratio is changed from 1/6 to 1/5.99.
Rev. 0.2
- 48 -
2014/06