AK4137EQ Datasheet, PDF (38/65 Pages) Asahi Kasei Microsystems – 32bit SRC with PCM/DSD conversion

[AK4137]
In serial control mode (PSN pin = “L”), the BYPS bit selects SRC bypass mode and SRC mode.
The default value of the BYPS bit is “0” (SRC mode).
CM3 CM2 CM1 CM0 BYPS
Mode
pin pin pin pin bit
Master /
Slave
OMCLK Input
(Note 24)
MCKO
Output
FSO
PCM
DSD
0
L
L
L
L
0
Master
256FSO
256FSO 8k  192kHz
1
L
L
L
H
0
Master
384FSO
384FSO 8k  96kHz
64fs
2
L
L
H
L
0
3
L
L
H
H
0
4
L
H
L
L
0
Master
Master
Slave
512FSO
768FSO
Not used.
(Note 23)
512FSO
768FSO
-
8k  96kHz
8k  48kHz
8k  768kHz
128fs
256fs
(48k, 44.1k)
5
L
H
L
H
0
Master
128FSO
(Note 25)
64fs, 128fs
128FSO 8k  384kHz
(48k, 44.1k)
6
L
H
H
L
0
Slave (Bypass)
Not used.
-
-
-
7
L
H
H
H
0 Master (Bypass)
(Note 23)
8
H
-
-
-
0
Master
64FSO
64fs
64FSO 8k  768kHz
(48k, 44.1k)
9
L
L
L
L
1 Master (Bypass)
10
L
L
L
H
1 Master (Bypass)
11
L
L
H
L
1 Master (Bypass)
12
L
L
H
H
1 Master (Bypass)
13
L
H
L
L
1
Slave (Bypass)
Not used.
-
-
-
14
L
H
L
H
1 Master (Bypass)
(Note 23)
15
L
H
H
L
1
Slave (Bypass)
16
L
H
H
H
1 Master (Bypass)
17
H
-
-
-
1 Master (Bypass)
Note 23. Use for a clock input or connect to DVSS. In Mode 6-15, OMCLK/XTI input is ignored
internally.
Note 24. In SRC mode, even input port clocks: ILRCK and IBICK are stopped, the AK4137 keeps outputting
divided clock of the XTI/OMCLK inputs if the device is in master mode and a clock input to the
XTI/OMCLK pin is being kept. In SRC bypass mode of master mode, ILRCK is input through and
output from the OLRCK pin, and BICK is input through and output from the OBICK pin. Therefor the
OLRCK output will be stopped if ILRCK clock at the input port is stopped, and the OBICK will be
stopped if IBICK clock at the input port is stopped.
Note 25. TDM output mode is not supported in this mode.
Table 3. Output PORT Master/Slave/ Bypass Mode Control ( PSN pin = “L”)
Rev. 0.2
- 38 -
2014/06