AK4137EQ Datasheet, PDF (19/65 Pages) Asahi Kasei Microsystems – 32bit SRC with PCM/DSD conversion

[AK4137]
Parameter
Symbol
Min.
Typ.
Max. Unit
Audio Interface Timing
Input PORT (Slave mode)
IBICK Period Normal speed mode
tBCK 1/256 FSIN
ns
Double speed mode
tBCK 1/128 FSID
ns
Quad speed mode
tBCK 1/64 FSIQ
ns
Oct speed mode
tBCK 1/64 FSIO
ns
Hexa speed mode
tBCK 1/64 FSIH
ns
IBICK Pulse Width Low
tBCKL
7
ns
Pulse Width High
tBCKH
7
ns
ILRCK Edge to IBICK “↑”(Note 15)
tLRB
5
ns
IBICK “↑” to ILRCK Edge (Note 15)
tBLR
5
ns
SDTI Hold Time from IBICK “↑”
tSDH
5
ns
SDTI Setup Time to IBICK “↑”
tSDS
5
ns
DSD Audio Interface Timing (64 mode)
DCLK Period
tDCK
-
1/64FSIN
-
ns
DCLK Pulse Width Low
tDCKL
160
ns
DCLK Pulse Width High
tDCKH
160
ns
DCLK Edge to DSDL/R
tDDD
20
20
ns
DSD Audio Interface Timing (128 mode)
DCLK Period
tDCK
-
1/128FSIN
-
ns
DCLK Pulse Width Low
tDCKL
80
ns
DCLK Pulse Width High
tDCKH
80
ns
DCLK Edge to DSDL/R
tDDD
10
10
ns
DSD Audio Interface Timing (256 mode)
DCLK Period
tDCK
-
1/256FSIN
-
ns
DCLK Pulse Width Low
tDCKL
40
ns
DCLK Pulse Width High
tDCKH
40
ns
DCLK Edge to DSDL/R
tDDD
5
5
ns
Input PORT (TDM256 slave mode)
IBICK Period
tBCK
81
ns
IBICK Pulse Width Low
tBCKL
32
ns
Pulse Width High
tBCKH
32
ns
ILRCK Edge to IBICK “↑”
(Note 15)
tLRB
20
ns
IBICK “↑” to ILRCK Edge
(Note 15)
tBLR
20
ns
SDTI Hold Time from IBICK “↑”
tSDH
20
ns
SDTI Setup Time to IBICK “↑”
tSDS
20
ns
Input PORT (TDM512 slave mode)
IBICK Period
tBCK
40
ns
IBICK Pulse Width Low
tBCKL
16
ns
Pulse Width High
tBCKH
16
ns
ILRCK Edge to IBICK “↑”
(Note 15)
tLRB
10
ns
IBICK “↑” to ILRCK Edge
(Note 15)
tBLR
10
ns
SDTI Hold Time from IBICK “↑”
tSDH
10
ns
SDTI Setup Time to IBICK “↑”
tSDS
10
ns
Rev. 0.2
- 19 -
2014/06