AK4137EQ Datasheet, PDF (46/65 Pages) Asahi Kasei Microsystems – 32bit SRC with PCM/DSD conversion

[AK4137]
■ System Reset
Bringing the PDN pin = “L” sets the AK4137 power-down mode and initializes digital filters. The
AK4137 should be reset once by bringing the PDN pin = “L” upon power-up. When the PDN pin is “L”,
the SDTO output is “L”. It takes 23ms (max) to output SDTO data after power-down state is released
by a clock input. Until then, the SDTO pin outputs “L”. The internal SRC circuit is powered up on an
edge of ILRCK after the internal regulator is powered up.
Case 1
External clocks
(Input port) ^{Don’t care}
SDTI
Don’t care
External clocks
(Output port)
Don’t care
Input Clocks 1
Input Data 1
Output Clocks 1
Input Clocks 2
Input Data 2
Output Clocks 2
Don’t care
Don’t care
Don’t care
PDN
(1)
< 23ms
(Internal state) Power-down
LDO Up&
fs detection &GD
Normal
operation
(1)
< 23ms
PD
fs
LDO Up&
detection &GD
Normal
operation
Power-down
SDTO
“0” data
Normal data
“0” data
Normal data “0” data
SRCE_N
Figure 39. System Reset 1
The setting of the PSN, CM3-0, OBIT1-0, TDM, ODIF1-0, IDIF2-0, CAD1-0 pins must be changed
during the PDN pin is “L”. The SRCE_N pin outputs “H” while PDN pin = “L”. If the internal regulator is
normal operation and ratio detection is completed, SRC data is output from the SDTO pin after a rising
edge of the PDN pin.
Case 2
External clocks
(Input port)
SDTI
External clocks
(Output port)
PDN
(No Clock)
(Don’t care)
(Don’t care)
(Internal state) Power-down
LDO Up
ILCK
SDTO
“0” data
Input Clocks
Input Data
Output Clocks
Don’t care
Don’t care
Don’t care
(1)
< 21ms
fs detection
& GD
Normal
operation
Power-down
Normal data “0” data
SRCE_N
Figure 40. System Reset 2
Rev. 0.2
- 46 -
2014/06