AK4137EQ Datasheet, PDF (47/65 Pages) Asahi Kasei Microsystems – 32bit SRC with PCM/DSD conversion

[AK4137]
■ Internal Reset Function for Clock Change
Clock change timing is shown in Figure 41 and Figure 42. When changing the clock, the AK4137
should be reset by the PDN pin in parallel control mode and it should be reset by the PDN pin or RSTN
bit in serial control mode.
External clocks
(input port
or output port)
Clocks 1
(Don’t care) Clock 2
PDN
(interlal state) normal operation ^Power
down
< 23msec
LDO ON &
fs detection & GD
normal operation
SDTO
normal data
Note26
normal data
SMUTE (Note27,
recommended)
0dB
Att.Level
-dB
1024/fso
1024/fso
Figure 41. Sequence of Changing Clocks (Parallel Control Mode, PSN pin= “H”)
Note 26. The data on SDTO may cause a clicking noise. To prevent this, set “0” to the SDTI more than
1024/fs (GD) before the PDN pin changes to “L”. It makes the data on SDTO remain as “0”.
Note 27. SMUTE can also remove the clicking noise (Note 26).
External clocks
(input port
or output port)
Clocks 1
(Don’t care) Clock 2
PDN
(interlal state) normal operation
SDTO
normal data
Power
down
Note 28
< 23msec
LDO ON &
fs detection & GD
Note 31
normal operation
normal data
SMUTE (Note 29,
recommended)
0dB
Att.Level
-dB
1024/fso
1024/fso
Figure 42. Sequence of Changing Clocks (Serial Control Mode, PSN pin= “L”)
Note 28. The data on SDTO may cause a clicking noise. To prevent this, set “0” to the SDTI more than
1024/fs (GD) before the PDN pin changes to “L”. It makes the data on SDTO remain as “0”.
Note 29. SMUTE can also remove the clicking noise (Note 28).
Note 30. The digital block except serial control interface and registers is powered-down. The internal
oscillator and regulator are not powered-down.
Note 31. It is the total time of “0.5/FSI+8/FSI(O)+156/FSO” or “1.5/FSI+8/FSI(O)+156/FSO”. (FSI(O) is
lower frequency between FSI and FSO)
Rev. 0.2
- 47 -
2014/06