AK4137EQ Datasheet, PDF (22/65 Pages) Asahi Kasei Microsystems – 32bit SRC with PCM/DSD conversion

[AK4137]
Parameter
Symbol Min. Typ. Max. Unit
Control Interface Timing
CCLK Period
CCLK Pulse Width High
CCLK Pulse Width Low
CDTI Setup Time
CDTI Hold Time
CSN High Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
tCCK
200
tCCKH
80
tCCKL
80
tCDS
50
tCDH
50
tCSW
150
tCSS
50
tCSH
50
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
CCLK “↓” to CDTO
CSN “↑” to CDTO “Hi-Z”
Control Interface Timing (I²C Bus):
tDCD
tCCZ
45
ns
70
ns
SCL Clock Frequency
fSCL
-
400 kHz
Bus Free Time Between Transmissions
tBUF
1.3
-
s
Start Condition Hold Time
(prior to first clock pulse)
tHD:STA
0.6
-
s
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
tLOW
1.3
tHIGH
0.6
tSU:STA
0.6
-
s
-
s
-
s
SDA Hold Time from SCL Falling (Note 19)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
tHD:DAT
0
tSU:DAT
0.1
tR
-
-
s
-
s
0.3 s
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
tF
-
tSU:STO
0.6
0.3 s
-
s
Pulse Width of Spike Noise
tSP
0
50
ns
Suppressed by Input Filter
Capacitive load on bus
Cb
-
400 pF
Note 19. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Rev. 0.2
- 22 -
2014/06