AK4137EQ Datasheet, PDF (51/65 Pages) Asahi Kasei Microsystems – 32bit SRC with PCM/DSD conversion

[AK4137]
I²C-bus Control Mode (I2C pin = “H”)
The AK4137 supports High speed mode I2C-bus (max: 400kHz).
WRITE Operation
Figure 46 shows the data transfer sequence of the I2C-bus mode. All commands are preceded by
START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates START
condition (Figure 52). After the START condition, a slave address is sent. This address is 7 bits long
followed by the eighth bit that is a data direction bit (R/W). The most significant six bits of the slave
address are fixed as “001001”. The next bit is CAD0 (device address bit). This bit identifies the
specific device on the bus. The hard-wired input pin (CAD0 pin) set these device address bits (Figure
47). If the slave address matches that of the AK4137, the AK4137 generates an acknowledge and the
operation is executed. The master must generate the acknowledge-related clock pulse and release
the SDA line (HIGH) during the acknowledge clock pulse (Figure 53). R/W bit = “1” indicates that the
read operation is to be executed. “0” indicates that the write operation is to be executed.
The second byte consists of the control register address of the AK4137. The format is MSB first, and
those most significant 3-bits are fixed to zeros (Figure 48). The data after the second byte contains
control data. The format is MSB first, 8bits (Figure 49). The AK4137 generates an acknowledge after
each byte is received. Data transfer is always terminated by STOP condition generated by the master.
A LOW to HIGH transition on the SDA line while SCL is HIGH defines STOP condition (Figure 52).
The AK4137 can execute multiple one byte write operations in a sequence. After receipt of the third
byte the AK4137 generates an acknowledge and awaits the next data. The master can transmit more
than one byte instead of terminating the write cycle after the first data byte is transferred. After
receiving each data packet the internal 6-bit address counter is incremented by one, and the next
data is automatically taken into the next address. If the address exceeds 06H prior to generating a
stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW
state of the data line can only change when the clock signal on the SCL line is LOW (Figure 54)
except for the START and STOP conditions.
S
T
S
A
R/W="0"
T
R
O
T
P
SDA
S lave
S _Address
S ub
A ddress(n)
Data(n)
Data(n+1)
Data(n+x)
P
A
A
A
A
A
A
C
C
C
C
C
C
K
K
K
K
K
K
Figure 46. Data Transfer Sequence at the I²C-Bus Mode
0
0
1
0
0 CAD1 CAD0 R/W
Figure 47. The First Byte
0
0
0
A4
A3
A2
A1
A0
Figure 48. The Second Byte
D7 D6 D5 D4 D3 D2 D1 D0
Figure 49. Byte Structure after the second byte
Rev. 0.2
- 51 -
2014/06