AK7744VT Datasheet, PDF (47/50 Pages) Asahi Kasei Microsystems – 24bit 3ch ADC + 24bit 4ch DAC with Audio DSP

[ASAHI KASEI]
[AK7744]
(2) Peripheral circuit
1) Ground and power supply
A To minimize digital noise coupling, AVDD and DVDD should be individually de-coupled at the AK7744.
System analog power is supplied to AVDD. Generally, the power supply and ground wires must be connected
separately for the analog and digital sections. Connect them at a position close to the power source on the PC board.
Decoupling capacitors and small ceramic capacitors should be connected as close as possible to the AK7744
2) Reference voltage
The input voltage difference between the VREFH pin and the AVSS pin determines the full scale of analog input,
while the potential difference between the VREFH pin and the AVSS pin determines the full scale of the analog
output. Normally, connect AVDD to VREFH, and connect 0.1µF ceramic capacitors from them to AVSS. To shut out
high frequency noise, connect a 0.1µF ceramic capacitor in parallel with an appropriate 10µF electrolytic capacitor
between this pin and AVSS. The ceramic capacitor in particular should be connected as close as possible to the pin.
To avoid coupling to the AK7744, digital signals and clock signals should be kept away as far as possible from the
VREFH pin.
VCOM is used as the common voltage of the analog signal.To shut out high frequency noise, connect a 0.1µF
ceramic capacitor in parallel with an appropriate 10µF electrolytic capacitor between this pin and AVSS. The
ceramic capacitor should be connected as close as possible to the pin. Do not lead current from the VCOM pin.
3) Analog input
Analog input signals are applied to the modulator through the differential input pins or single-ended pins of
each channel selected by the input selector. When using the differential inputs, this voltage is equal to the differential
voltage between AIN+ and AIN- (∆VAIN=(AIN+)-(AIN-)), and the input range is ±FS= ±(VREFH-AVSS)×(2.0/3.3).
When VREFH = 3.3V and AVSS = 0V, the input range is within ±2.0Vpp. When using single-ended inputs, this input
range is FS = (VREFH-AVSS)×(2.0/3.3). When VREFH = 3.3V and AVSS = 0V, the input range is within 2.0Vpp
the output code format is given in terms of 2's complements.
The analog source voltage to the AK7744 is +3.3V(Typ.). Voltage of AVDD+0.3V or more, voltage of
AVSS-0.3V or less, and current of 10 mA or more must not be applied to analog input pins
(AINL+,AINL-,AINR+,AINR-,AINL1,AINR1,AINL2,AINR2,AINL3,AINR3,AINL4,AINR4,AINL5,AINR5,
A2IN+,A2IN-,A2IN1,VREFH) Excessive current will damage the internal protection circuit and will cause
latch-up, thereby damaging the IC. Accordingly, if the surrounding analog circuit voltage is ±15 V, the analog input
pins must be protected from high-voltage signals.
22u
+
10k
Signal
10k
+10V
-
+
-1 0 V
10k
10k
-
+
+
NJM5532D ^4.7u
+
Vop = VA+ = 3.3V
4.7u
2.00Vpp
AIN+
AIN-
2.00Vpp
Fig. 1 Example of input buffer circuit (differential input)
<MS0167-E-00>
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2002/10