AK7744VT Datasheet, PDF (26/50 Pages) Asahi Kasei Microsystems – 24bit 3ch ADC + 24bit 4ch DAC with Audio DSP

[ASAHI KASEI]
[AK7744]
(4) Resetting
The AK7744 has two reset pins: INIT_RESET and S_RESET .
The INIT_RESET pin is used to set up VREF and initialize the AK7744, as shown in "Power supply startup
sequence section 3)."
The system is reset when S_RESET =”L”. (Description of "reset" is for "system reset".)
During a system reset, a program write operation is normally performed (except for write operation during
running).
During the system reset phase, the ADC and DAC sections are also reset. (The digital section of ADC output is
MSB first 00000h and the analog section of DAC output is AVDD/2). However, VREF will be active, LRCLK and
BITCLK in the master mode will be inactive
The system reset is released by setting S_RESET to "H", whichl activates the internal counter. This counter
generates LRCLK and BITCLK in the master mode: however, a problem may occur when a clock signal is generated.
When the system reset is released in slave mode, internal timing will be actuated in synchronization with rising edge
"Ç" of LRCLK (when the standard input format is used). Timing between the external and internal clocks is adjusted
at this time. If the phase difference in LRCLK and internal timing is within about -1/16 to 1/16 of the input sampling
cycle (1/fs) during the operation, the operation is performed with internal timing remaining unchanged. If the phase
difference exceeds the above range, the phase is adjusted by synchronizing the "Ç" of LRCLK (when the standard
input format is used). This prevents synchronization failure with the external circuit. For some time after returning to
the normal state after loss of synchronization, normal data will not be valid. It should change the frequency of clock,
SMODE or Analog input selector, while the system is in reset.
When S_RESET is set to “H”, the reset state is cancelled, and an internal DRAM clear is executed on the rising
edge of LRCLK. It takes 8Fs (167usec at fs=48kHz) to clear the internal DRAM.
The ADC section can output 516-LRCLK after its internal counter has started. (The internal counter starts at the first
rising edge of LRCLK in master mode. In slave mode, it starts 2 LRCLKs after the release of system reset. )
The AK7744 performs normal operation when S_RESET is set to "H".
When INIT_RESET or S_RESET changes, the status of the DAC section also changes to Power down or
Release mode, and it causes a click noise on the output. In this case, the SMUTE function is not effective; an external
mute circuit is necessary to avoid any click noise.
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2002/10