AK7744VT Datasheet, PDF (27/50 Pages) Asahi Kasei Microsystems – 24bit 3ch ADC + 24bit 4ch DAC with Audio DSP

[ASAHI KASEI]
[AK7744]
(5) System clock
The required system clock is XTI (384fs/512fs), LRCLK (fs) and BITCLK (64 fs) in the slave mode, and is XTI
(384 fs/512 fs) in the master mode. LRCLK corresponds to the standard digital audio rate (32 kHz, 44.1 kHz, and
48 kHz).
Fs
32.0kHz
44.1kHz
48.0kHz
XTI(Master Clock)
512fs
384fs
16.3840MHz 12.2880MHz
22.5792MHz 16.9344MHz
24.576MHz 18.4320MHz
BITCLK
64fs
2.0480MHz
2.8224MHz
3.0720MHz
5-1) Master clock (XTI pin)
The master clock is obtained by connecting a crystal oscillator between the XTI pin and XTO pin or by inputting an
external clock into the XTI pin while the XTO pin is left open.
5-2) Slave mode
The required system clock is XTI, LRCLK (1 fs) and BITCLK (48/64 fs).
The master clock (XTI) and LRCLK must be synchronized, but the phase is not critical.
5-3) Master mode
The required system clock is XTI (384fs/512fs). When the master clock (XTI) is input, LRCLK (1 fs) and BITCLK
(64 fs) will be outputted from the internal counter synchronized with the XTI. LRCLK and BITCLK will not be
active during initial reset ( INIT_RESET ="L") and system reset ( S_RESET ="L").
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2002/10