AK7744VT Datasheet, PDF (28/50 Pages) Asahi Kasei Microsystems – 24bit 3ch ADC + 24bit 4ch DAC with Audio DSP

[ASAHI KASEI]
[AK7744]
(6) Audio data interface (internal connection mode )
The serial audio data pins SDIN,SDINA1,SDINA2,SDOUT,SDOUTA1,SDOUTA2,SDOUTD1 and SDOUTD2 are
interfaced with the external system, using LRCLK and BITCLK. The ports SDINA1, SDINA2, SDOUTA1,
SDOUTA2, SDOUTD1 and SDOUTD2 are not normally used. These ports are controlled via registers. ( See the
block diagram on page.2 and the control register setting section at page 28.)
The data format is MSB-first 2's complement. Normally, the input/output format, in addition to the standard format
used by AKM, can be changed to the I2S compatible mode by setting the control register “CONT0 DIF (D5) to 1”.
(In this case, all input/output audio data pin interface are in the I2S compatible mode.)
The input SDIN,SDINA1 and SDINA2 formats are MSB justified 24-bit at initialization. Setting the control registers
CONT0: DIF1 (D4), DIF0(D3) will cause these ports to be compatible with LSB justified 24-bit, 20-bit and 16-bit.
(SDINA is fixed at 24-bit MSB justified only.) (Note: CONT0 DIF(D5)=0). However, individual setting of SDIN,
SDINA1 and SDINA2 is not allowed. The output SDOUT, SDOUTA1, SDOUTA2, SDOUTD1 and SDOUTD2
are fixed at 24-bit MSB justified only.
In slave mode BITCLK corresponds to not only 64fs but also 48fs. 64fs is the recommended mode. Following form
ats describe 64fs examples.
6-1) Standard input format (DIF = 0: default set value)
a) Mode 1 (DIF1, DIF0 = 0,0: default set value)
LRCLK
Left ch
Right ch
BITCLK
31 30 29
SDIN,SDINA1, _{M 22 21}
SDINA2
10 9 8 7 6 5 4 3 2 1 0 31 30 29
21L
M 22 21
10 9 8 7 6 5 4 3 2 1 0
21L
M : MSB, L : LSB
* When you want to input the MSB-justified 20-bit data into SDIN, SDINA input four "0" following the LSB.
b) Mode 2, Mode 3, Mode 4
LRCLK
Left ch
Right ch
BITCLK
31 30
23 22 21 20 19 18 17 16 15 1 0 31 30
23 22 21 20 19 18 17 16 15
SDIN,SDINA1, _{Don't Care M 22 21 20 19 18 17 16 15}
SDINA2
SDIN,SDINA1 Don't Care
SDINA2
M 18 17 16 15
SDIN,SDINA1 Don't Care
M
SDINA2
1 L Don't Care M 22 21 20 19 18 17 16 15
1 L Don't Care
M 18 17 16 15
1 L Don't Care
M
M : MSB, L : LSB
SDIN,SDINA1,SDINA2
SDIN,SDINA1,SDINA2
SDIN,SDINA1,SDINA2
Mode2 : (DIF1,DIF0)=(0,1) LSB justified 24-bit
Mode3 : (DIF1,DIF0)=(1,0) LSB justified 20-bit
Mode4 : (DIF1,DIF0)=(1,1) LSB justified 16-bit
10
1L
1L
1L
<MS0167-E-00>
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2002/10