AK7744VT Datasheet, PDF (40/50 Pages) Asahi Kasei Microsystems – 24bit 3ch ADC + 24bit 4ch DAC with Audio DSP

[ASAHI KASEI]
[AK7744]
7-3) Write during RUN phase
7-3-a) CRAM rewrite preparation and write (during RUN phase)
This function is used to rewrite CRAM (coefficient RAM) during program execution. After inputting the
command code, you can input a maximum of 16 data bytes of a continuous address you want to rewrite, then input the
write command code and rewrite the leading address. Every time the RAM address to be rewritten is specified, the
contents of RAM are rewritten. The following is an example to show how five data bytes from address "10" of the
coefficient RAM are rewritten:
Coefficient RAM execution address 7 8 9 10 11 13 16 11 12 13 14 15
ÈÈ
ÈÈÈ
Rewrite position
} }Ç
} }}
Note that address "13" is not executed until address "12" is rewritten.
Data transfer procedure
* Preparation for rewrite
* Rewrite
c Command code
d Data
e Data
c Command code
d Address upper
e Address lower
A8h ( 1 0 1 0 1 0 0 0 )
( D15 . . . . D8 )
( D7 . . . . . D0 )
A4h ( 1 0 1 0 0 1 0 0 )
( 0 0 0 0 0 0 0 A8 )
(A7 . . . . A0 )
S_RESET
RQ
SCLK
SI
RDY
SO
10101000 D15 **** D0
10100100 A15 **** A0
AL
max 200ns
Longer of (16-n) x 2 MCL
K
(n: number of data) and AL
RDYLG
Note: The RDY signal will go to high within the maximum of two LRCLKs if the
RDYLG width is programmed to ensure a new address to be rewritten within one
li
l
CRAM rewriting preparation and writing
<MS0167-E-00>
- 40 -
2002/10