AK7744VT Datasheet, PDF (35/50 Pages) Asahi Kasei Microsystems – 24bit 3ch ADC + 24bit 4ch DAC with Audio DSP

[ASAHI KASEI]
[AK7744]
7-1-e) External conditional jump code write (during reset phase)
Two bytes of data are used to perform offset is external conditional jump operations. The data can be entered during
both the reset and operation phases, and the input data are set to the specified register at the leading edge of the
LRCLK. When all data bits have been transferred, the RDY terminal goes to "L". Upon write completion, it goes to
"H". A jump command will be executed if there is any one agreement between "1" of each bit of external condition
code 8 bits (soft set) plus 1 bit (hard set) at the external input terminal JX and "1" of each bit of the IFCON field. The
data during the reset phase can be written only before release of the reset, after all data has been transferred. RQ
Transition from "L" to "H" in the write operation during the reset phase must be executed after three LRCLK in the
slave mode or one LRCLK in master mode, respectively, from the trailing edge of the LRCLK after release of the
reset. Then the RDY goes to "H" after capturing the rise of the next LRCLK. A write operation from the
microcomputer is disabled until the RDY goes to "H". The IFCON field provides external conditions written on the
program. It resets to 00h by INIT_RESET =”L”, however, it remains previous condition even S_RESET =”L”.
Note: It should be noted that the LRCLK phase is inverted in the I2S-compatible state.
7
0 JX
External condition code „„„„„„„„†
Ç
Check if there is any one agreement between the bit specified in IFCON and
"1" in the external condition code
16
È
8
IFCON field ‹‹‹‹‹‹‹‹
Data transfer procedure
c Command code
d Code data
C4h ( 1 1 0 0 0 1 0 0)
(D7 . . . . . D0)
S_RESET
SCLK
SI
SO
RQ
LRCLK
RDY
11000100 D7 **** D0
L ch R ch
2LRCLK(max)
Timing for external conditional jump write operation (during reset phase)
<MS0167-E-00>
- 35 -
2002/10